Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813899
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver 3. Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives 4. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Simulating the Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signals
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench
2.5. Hardware Testing x
2.5.1. Test Procedure
1. Quick Start Guide
2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver
3. Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
4. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

2.4.1. Testbench

Figure 7. Block Diagram of the 10/100/1000Mb Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver Simulation Testbench
Note: SYSPLL IP is not instantiated in DUT when data clocking mode selected is PMA (Native PHY). Testbench simulation tests the basic checks with packets, thus it does not qualify PMA reconfiguration interface.

A successful testbench sends five packets and receives the same number of packets. The following sample output illustrates the excerpt of the output:

Figure 8. Simulation Test Result of VCS* MX Simulator 
Statistics MAC Tx Path

      — Frames sent in TX path total:      5
      — Tx_good_sent:        5
      — Tx_vlan_sent:         0
      — Tx_stack_vlan_sent:      0
      — Payload_err_sent:        0

Statistics MAC Rx Path — Loopback Test

      — Rx_good_rcvd:        5
      — Rx_vlan_rcvd:         0
      — Rx_stack_vlan_rcvd:      0
      — Rx_fifo_overflow_rcvd:   0
      — Rx_payload_err_rcvd:     0
      — Rx_crc_err_rcvd:         0

-- Loopback Simulation Ended with no Error

- -------------------------------------------------------------------------- -

End of Simulation — Break
Level Two Title