Hard Processor System Component Reference Manual: Agilex™ 5 SoCs

ID 813752
Date 8/09/2024
Public
Document Table of Contents

2.4.2. PLL Clocks

The PLL Clock tab is comprised of three subsections:
  • Main PLL Output
  • Peripheral PLL Output
  • MPU Clocks
  • NOC Clocks
  • Peripheral Clocks
  • HPS-to-FPGA User Clocks
Figure 12.  Platform Designer PLL Clocks Sub-tab