Hard Processor System Component Reference Manual: Agilex™ 5 SoCs

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ID 813752
Date 11/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to the Agilex™ 5 Hard Processor System Component 2. Configuring the Agilex™ 5 Hard Processor System Component 3. Simulating the Agilex™ 5 HPS Component 4. Design Guidelines 5. Document Revision History for the Hard Processor System Component Reference Manual Agilex™ 5 SoCs
1. Introduction to the Agilex™ 5 Hard Processor System Component x
1.1. Release Notes 1.2. Micro Processor Unit 1.3. Application Processor Subsystem 1.4. Peripheral Subsystem 1.5. CoreSight* Debug Components 1.6. Interconnect 1.7. FPGA Bridges 1.8. Introduction to the Agilex™ 5 Hard Processor System Component Revision History
1.1. Release Notes x
1.1.1. HPS IP 5.1.0 1.1.2. HPS IP 4.0.0
2. Configuring the Agilex™ 5 Hard Processor System Component x
2.1. Parameterizing the HPS Component 2.2. HPS-FPGA Interfaces 2.3. SDRAM 2.4. HPS Clocks, Reset, Power 2.5. I/O Delays 2.6. Pin Mux and Peripherals 2.7. Generating and Compiling the HPS Component 2.8. Using the Address Span Extender Component 2.9. Configuring the Agilex™ 5 Hard Processor System Component Revision History
2.2. HPS-FPGA Interfaces x
2.2.1. General 2.2.2. HPS FPGA Bridges 2.2.3. DMA Controller Interface 2.2.4. Interrupts
2.2.1. General x
2.2.1.1. Enable MPU Standby and Event Signals 2.2.1.2. Enable General Purpose Signals 2.2.1.3. Enable Debug APB* Interface 2.2.1.4. Enable System Trace Macrocell (STM) Hardware Events 2.2.1.5. Enable SWJ-DP JTAG Interface 2.2.1.6. Enable FPGA Cross Trigger Interface 2.2.1.7. Enable AMBA* Trace Bus (ATB)
2.2.2. HPS FPGA Bridges x
2.2.2.1. FPGA to HPS Subordinate 2.2.2.2. FPGA to SDRAM Subordinate 2.2.2.3. HPS to FPGA Manager 2.2.2.4. Lightweight HPS to FPGA Manager
2.2.4. Interrupts x
2.2.4.1. FPGA-to-HPS 2.2.4.2. HPS-to-FPGA
2.3. SDRAM x
2.3.1. Configurations for HPS IP 2.3.2. Configurations for HPS EMIF IP 2.3.3. Graphical Connections of HPS to HPS-EMIF 2.3.4. Configuration when using ECC 2.3.5. Supported Memory Protocols Among Device Families 2.3.6. IO96 Bank and Lane Usage for HPS EMIF 2.3.7. Quartus Report of I/O Bank Usage
2.4. HPS Clocks, Reset, Power x
2.4.1. Input Clocks 2.4.2. PLL Clocks 2.4.3. Power and Resets
2.4.1. Input Clocks x
2.4.1.1. External Clocks 2.4.1.2. FPGA-to-HPS Clocks 2.4.1.3. Peripheral FPGA Clocks
2.4.2. PLL Clocks x
2.4.2.1. Main PLL Output 2.4.2.2. Peripheral PLL Output 2.4.2.3. MPU Clocks 2.4.2.4. NOC Clocks 2.4.2.5. Peripheral Clocks 2.4.2.6. HPS-to-FPGA User Clocks
2.4.3. Power and Resets x
2.4.3.1. Power Configurations 2.4.3.2. Reset Signals
2.6. Pin Mux and Peripherals x
2.6.1. Pin Mux GUI 2.6.2. EMAC PTP Interface 2.6.3. HPS I/O Open Drain 2.6.4. HPS I/O Locations
2.6.1. Pin Mux GUI x
2.6.1.1. Auto-Place IP 2.6.1.2. Advanced
2.6.1.1. Auto-Place IP x
2.6.1.1.1. Options for NAND, SDMMC, TRACE, TPIU, EMAC
2.6.1.1.1. Options for NAND, SDMMC, TRACE, TPIU, EMAC x
2.6.1.1.1.1. HPS IO Placement Priority
2.6.1.2. Advanced x
2.6.1.2.1. Advanced IP Placement 2.6.1.2.2. Advanced FPGA Placement
3. Simulating the Agilex™ 5 HPS Component x
3.1. Simulation Flows 3.2. Running the Simulation of the Design Examples 3.3. Clock and Reset Interface 3.4. FPGA-to-HPS AXI* Subordinate Interface 3.5. FPGA-to-SDRAM AXI* Subordinate Interface 3.6. HPS-to-FPGA AXI* Initiator Interface 3.7. Lightweight HPS-to-FPGA AXI* Initiator Interface 3.8. Simulating the Agilex™ 5 HPS Component Revision History
3.1. Simulation Flows x
3.1.1. Setting Up the HPS Component for Simulation 3.1.2. Generating the HPS Simulation Model in Platform Designer 3.1.3. RTL Simulation Setup Scripts
3.1.3. RTL Simulation Setup Scripts x
3.1.3.1. QuestaSim* Simulation Steps 3.1.3.2. Cadence® Xcelium* Simulation Steps 3.1.3.3. Synopsys* VCS* Simulation Steps 3.1.3.4. Synopsys* VCS* MX Simulation Steps 3.1.3.5. Aldec® Riviera-PRO* Simulation Steps
3.2. Running the Simulation of the Design Examples x
3.2.1. HPS-to-FPGA Bridge (H2F) 3.2.2. Lightweight HPS-to-FPGA (LWH2F) 3.2.3. FPGA-to-HPS Bridge (F2H) 3.2.4. FPGA-to-SDRAM Bridge (F2SDRAM)
3.2.1. HPS-to-FPGA Bridge (H2F) x
3.2.1.1. Steps to run the Simulation in Questa* Intel® FPGA Edition 3.2.1.2. Steps to run the Simulation in Synopsys* VCS*
3.2.2. Lightweight HPS-to-FPGA (LWH2F) x
3.2.2.1. Steps to run the Simulation in Questa* Intel® FPGA Edition 3.2.2.2. Steps to run the Simulation in Synopsys* VCS*
3.2.3. FPGA-to-HPS Bridge (F2H) x
3.2.3.1. Steps to run the Simulation in Questa* Intel® FPGA Edition 3.2.3.2. Steps to run the Simulation in Synopsys* VCS*
3.2.4. FPGA-to-SDRAM Bridge (F2SDRAM) x
3.2.4.1. Steps to run the Simulation in Questa* Intel® FPGA Edition 3.2.4.2. Steps to run the Simulation in Synopsys* VCS*
3.3. Clock and Reset Interface x
3.3.1. Clock Interface 3.3.2. Reset Interface
4. Design Guidelines x
4.1. HPS System Reset Considerations 4.2. Design Guidelines Revision History
1. Introduction to the Agilex™ 5 Hard Processor System Component
2. Configuring the Agilex™ 5 Hard Processor System Component
3. Simulating the Agilex™ 5 HPS Component
4. Design Guidelines
5. Document Revision History for the Hard Processor System Component Reference Manual Agilex™ 5 SoCs

2.2.4.2. HPS-to-FPGA

Table 10.   HPS-to-FPGA Interface and Parameter Descriptions
Parameter Name Parameter Description Interface Name
Enable Clock Peripheral Interrupts

Enables interface for HPS clock manager and MPU wake-up interrupt signals to the FPGA

hps2fpga_clkmgr_interrupt

Enable DMAC Interrupts

Enables interface for HPS DMA channels interrupt and DMA abort interrupt to the FPGA

hps2fpga_dmac0_interrupt

hps2fpga_dmac0_ch0_interrupt

hps2fpga_dmac0_ch1_interrupt

hps2fpga_dmac0_ch2_interrupt

hps2fpga_dmac0_ch3_interrupt

hps2fpga_dmac0_cmreg_interrupt

hps2fpga_dmac1_interrupt

hps2fpga_dmac1_ch0_interrupt

hps2fpga_dmac1_ch1_interrupt

hps2fpga_dmac1_ch2_interrupt

hps2fpga_dmac1_ch3_interrupt

hps2fpga_dmac1_cmreg_interrupt

Enable EMAC Interrupts

Enables interface for HPS Ethernet MAC controller interrupt to the FPGA. EMAC must be enabled in Pin Mux Tab before enabling interrupt.

hps2fpga_emac0_interrupt

hps2fpga_emac0_rx_interrupt

hps2fpga_emac0_tx_interrupt

hps2fpga_emac1_interrupt

hps2fpga_emac1_rx_interrupt

hps2fpga_emac1_tx_interrupt

hps2fpga_emac2_interrupt

hps2fpga_emac2_rx_interrupt

hps2fpga_emac2_tx_interrupt

Enable GPIO Interrupts

Enables interface for the HPS general purpose IO (GPIO) interrupt to the FPGA

hps2fpga_gpio0_interrupt

hps2fpga_gpio1_interrupt

Enable I2C-EMAC Interrupts

Enable the HPS peripheral interrupt for I2C EMAC to be driven into the FPGA fabric

hps2fpga_i2c_emac0_interrupt

hps2fpga_i2c_emac1_interrupt

hps2fpga_i2c_emac2_interrupt

Enable I2C Peripherals Interrupts

Enable the HPS peripheral interrupt for I2C0 to be driven into the FPGA fabric. The I2C must be enabled in the Pin Mux Tab before enabling interrupt

hps2fpga_i2c0_interrupt

hps2fpga_i2c1_interrupt

Enable L4 Timer Interrupts

Enables the HPS peripheral interrupt for L4 TIMER to be driven into the FPGA fabric.

hps2fpga_timer_l4sp0_interrupt

hps2fpga_timer_l4sp1_interrupt

Enable NAND Interrupts

Enables interface for the HPS NAND controller interrupt to the FPGA. The NAND IP Block must be enabled in Pin Mux Tab before enabling interrupt.

hps2fpga_nand_interrupt

Enable SYS Timer Interrupts

Enables the HPS peripheral interrupt for SYSTIMER to be driven into the FPGA fabric.

hps2fpga_timer_sys0_interrupt

hps2fpga_timer_sys1_interrupt

Enable SDMMC Interrupts

Enables interface for the HPS SD/eMMC controller interrupt to the FPGA. The SD/MMC IP Block must be enabled in Pin Mux Tab before enabling interrupt

hps2fpga_sdmmc_interrupt

Enable SPI Manager Interrupts

Enables interface for the HPS SPI manager controller interrupt to the FPGA. The SPI Manager IP Block must be enabled in Pin Mux Tab before enabling interrupt.

hps2fpga_spim0_interrupt

hps2fpga_spim1_interrupt

Enable SPI Subordinate Interrupts

Enables interface for the HPS SPI subordinate controller interrupt to the FPGA. The SPI IP Block must be enabled in Pin Mux Tab before enabling interrupt

hps2fpga_spis0_interrupt

hps2fpga_spis1_interrupt

Enable ECC/Parity_L1 Interrupts

Enables the HPS peripheral interrupt for ECC single and double bit error and L1 parity error to be driven into the FPGA fabric.

hps2fpga_ecc_serr_interrupt

Enable UART Interrupts

Enables interface for the HPS UART controller interrupt to the FPGA. The UART IP Block must be enabled in Pin Mux Tab before enabling interrupt.

hps2fpga_uart0_interrupt

hps2fpga_uart1_interrupt

Enable USB Interrupts

Enables interface for the HPS USB controller interrupt to the FPGA. The USB IP Block must be enabled in Pin Mux Tab before enabling interrupt.

hps2fpga_usb0_interrupt

hps2fpga_usb31_interrupt

Enable Watchdog Interrupts

Enables interface for the HPS watchdog interrupt to the FPGA

hps2fpga_wdog0_interrupt

hps2fpga_wdog1_interrupt

hps2fpga_wdog2_interrupt

hps2fpga_wdog3_interrupt

Enable I3C Peripherals Interrupts

Enable the HPS peripheral interrupt for I3C0 and I3C1 to be driven into the FPGA fabric. The I3C must be enabled in the Pin Mux Tab before enabling interrupt

hps2fpga_i3c_m_interrupt

hps2fpga_i3c_s_interrupt

Level Two Title