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2.1. Parameterizing the HPS Component
2.2. HPS-FPGA Interfaces
2.3. SDRAM
2.4. HPS Clocks, Reset, Power
2.5. I/O Delays
2.6. Pin Mux and Peripherals
2.7. Generating and Compiling the HPS Component
2.8. Using the Address Span Extender Component
2.9. Configuring the Agilex™ 5 Hard Processor System Component Revision History
2.2.1.1. Enable MPU Standby and Event Signals
2.2.1.2. Enable General Purpose Signals
2.2.1.3. Enable Debug APB* Interface
2.2.1.4. Enable System Trace Macrocell (STM) Hardware Events
2.2.1.5. Enable SWJ-DP JTAG Interface
2.2.1.6. Enable FPGA Cross Trigger Interface
2.2.1.7. Enable AMBA* Trace Bus (ATB)
3.1. Simulation Flows
3.2. Running the Simulation of the Design Examples
3.3. Clock and Reset Interface
3.4. FPGA-to-HPS AXI* Subordinate Interface
3.5. FPGA-to-SDRAM AXI* Subordinate Interface
3.6. HPS-to-FPGA AXI* Initiator Interface
3.7. Lightweight HPS-to-FPGA AXI* Initiator Interface
3.8. Simulating the Agilex™ 5 HPS Component Revision History
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Ixiasoft
2.3.6. IO96 Bank and Lane Usage for HPS EMIF
The following table describes the IO96 Bank and Lane Usage for the various memory protocols when using the HPS-EMIF.
Number of signals | 12 | 12 | 12 | 12 | 12 | 12 | 12 | 12 | ||
---|---|---|---|---|---|---|---|---|---|---|
Bank | 3A | |||||||||
Sub-Bank | 3A_T | 3A_B | ||||||||
Bank Lanes | BL7 | BL6 | BL5 | BL4 | BL3 | BL2 | BL1 | BL0 | ||
Protocol | Design | EMIFs | ||||||||
DDR4 | 1x16 | 1 | — | — | — | DQ[1] | AC2 | AC1 | AC0 | DQ[0] |
1x16_ECC | 1 | — | — | DQ[ECC] | DQ[1] | AC2 | AC1 | AC0 | DQ[0] | |
1x32 | 1 | — | DQ[3] | DQ[2] | DQ[1] | AC2 | AC1 | AC0 | DQ[0] | |
1x32_ECC | 1 | DQ[ECC] | DQ[3] | DQ[2] | DQ[1] | AC2 | AC1 | AC0 | DQ[0] | |
2x32 | 2 2 | — | DQ[3] | DQ[2] | DQ[1] | AC2 | AC1 | AC0 | DQ[0] | |
2x32_ECC | 22 | DQ[ECC] | DQ[3] | DQ[2] | DQ[1] | AC2 | AC1 | AC0 | DQ[0] | |
1x64 | — | Not Supported | ||||||||
1x64_ECC | — | Not Supported | ||||||||
DDR5 | 1x16 | 1 | — | — | — | — | AC1 | AC0 | DQ[0] | DQ[1] |
1x16_ECC | 1 | — | — | — | DQ[ECC] | AC1 | AC0 | DQ[0] | DQ[1] | |
2x16 | 1 | DQ[1] | DQ[0] | AC1 | AC0 | AC1 | AC0 | DQ[0] | DQ[1] | |
2x16_ECC | — | Not Supported | ||||||||
1x32 | 1 | — | — | DQ[3] | DQ[2] | AC1 | AC0 | DQ[0] | DQ[1] | |
1x32_ECC | 1 | — | DQ[ECC] | DQ[3] | DQ[2] | AC1 | AC0 | DQ[0] | DQ[1] | |
2x32 | 22 | — | — | DQ[3] | DQ[2] | AC1 | AC0 | DQ[0] | DQ[1] | |
2x32_ECC | 22 | — | DQ[ECC] | DQ[3] | DQ[2] | AC1 | AC0 | DQ[0] | DQ[1] | |
1x64 | — | Not Supported | ||||||||
1x64_ECC | — | Not Supported | ||||||||
LPDDR4/LPDDR5 |
1x16 | 1 | — | — | — | — | AC1 | AC0 | DQ[1] | DQ[0] |
2x16 | 1 | DQ[1] | DQ[0] | AC1 | AC0 | AC1 | AC0 | DQ[1] | DQ[0] | |
1x32 | 1 | DQ[3] | DQ[2] | — | — | AC1 | AC0 | DQ[1] | DQ[0] | |
2x32 | 22 | DQ[3] | DQ[2] | — | — | AC1 | AC0 | DQ[1] | DQ[0] | |
4x16 | 22 | DQ[1] | DQ[0] | AC1 | AC0 | AC1 | AC0 | DQ[1] | DQ[0] |
2 Uses two IOBanks (Banks 3A and 3B)