Hard Processor System Component Reference Manual: Agilex™ 5 SoCs

ID 813752
Date 8/09/2024
Public
Document Table of Contents

2.4.2.6. HPS-to-FPGA User Clocks

  • Turn on the Enable User0 Clock and Enable User1 Clock option to enable the H2F User<n> clock interface
  • H2F User0 Clock Source Select and H2F User1 Clock Source Select drop-down configure clock source for User0 Clock and User1 Clock
    • PeriphC3
    • MainC1
  • H2F User0 Clock Desired Frequency and H2F User1 Clock Desired Frequency to input desired frequency for User0 and User1 clock in value of 1 to 500MHz
Figure 18.  Platform Designer HPS-to-FPGA User Clocks Sub-window