Hard Processor System Component Reference Manual: Agilex™ 5 SoCs

ID 813752
Date 8/09/2024
Public
Document Table of Contents

2.4.2.3. MPU Clocks

The default core MPU frequencies are displayed in a table. MPU CCU Clock Divider and MPU Peripheral Clock Divider are not configurable, set to Div2 and Div4 by default.

Turning on Override MPU Clocks exposes the main PLL clocks desired frequency. You can configure the desired frequency by overriding the value of each main PLL frequency.

The clock manager has one ping-pong counter for Core0 and Core1, which goes to Arm* Cortex*-A55 MPU; therefore only a single clock is generated for Core0 and Core1.

Figure 15.  Platform Designer MPU Clocks Sub-window