Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs

ID 813671
Date 7/25/2024
Public
Document Table of Contents

2.2.13.3. Static Phase Error Calibration

In Agilex™ 5 devices, a static phase error calibration is initiated after power up calibration. This is done automatically to reduce the phase error between reference clock and feedback clocks.