Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs

ID 813671
Date 7/25/2024
Public
Document Table of Contents

2.2.3. PLL Locations

Figure 8. I/O PLL Locations in HSIO Bank

Within an HSIO bank, there is a top index sub-bank and a bottom index sub-bank placed near the edge of the die.

If one of the sub-banks is not available in the HSIO bank, the dedicated clock input and clock output pins for the I/O PLL located in this unbonded sub-bank are unavailable. However, you can still use the I/O PLL in the following scenarios by ensuring the VCCPT is powered up:

  • PLL cascading and reconfiguration are supported.
  • You may use any available regular I/O pins as clock input and clock output pins for this I/O bank I/O PLL.
If one of the sub-banks is not available in the HSIO bank, the fabric-feeding I/O PLL in this HSIO bank has only one pair of dedicated clock input pins which is from the available sub-bank. Reconfiguration is supported by this fabric-feeding I/O PLL.
Figure 9. Fabric-feeding I/O PLL location in HVIO Block