Visible to Intel only — GUID: ihm1673422453787
Ixiasoft
1. Agilex™ 5 Clocking and PLL Overview
2. Agilex™ 5 Clocking and PLL Architecture and Features
3. Agilex™ 5 Clocking and PLL Design Considerations
4. Clock Control Intel® FPGA IP Core
5. IOPLL Intel® FPGA IP Core
6. I/O PLL Reconfiguration
7. Document Revision History for the Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs
2.2.1. PLL Features
2.2.2. PLL Usage
2.2.3. PLL Locations
2.2.4. PLL Architecture
2.2.5. PLL Control Signals
2.2.6. PLL Feedback Modes
2.2.7. Clock Multiplication and Division
2.2.8. Programmable Phase Shift
2.2.9. Programmable Duty Cycle
2.2.10. PLL Cascading
2.2.11. PLL Input Clock Switchover
2.2.12. PLL Reconfiguration and Dynamic Phase Shift
2.2.13. PLL Calibration
3.1. Guidelines: Clock Switchover
3.2. Guidelines: Timing Closure
3.3. Guidelines: Resetting the PLL
3.4. Guidelines: Configuration Constraints
3.5. Clocking Constraints
3.6. IP Core Constraints
3.7. Guideline: Achieving 5% Duty Cycle for fOUT_EXT ≥ 300 MHz Using tx_outclk Port from LVDS SERDES Intel® FPGA IP
6.1. Release Information for EMIF Calibration IP
6.2. Implementing HSIO I/O PLL Reconfiguration using EMIF Calibration IP
6.3. Implementing HVIO I/O PLL Reconfiguration
6.4. Reconfiguration Guideline for I/O PLLs
6.5. Axilite Interface Ports in the EMIF Calibration IP
6.6. Address Bus and Data Bus Settings
Visible to Intel only — GUID: ihm1673422453787
Ixiasoft
2.2.3. PLL Locations
Figure 8. I/O PLL Locations in HSIO Bank
Within an HSIO bank, there is a top index sub-bank and a bottom index sub-bank placed near the edge of the die.
If one of the sub-banks is not available in the HSIO bank, the dedicated clock input and clock output pins for the I/O PLL located in this unbonded sub-bank are unavailable. However, you can still use the I/O PLL in the following scenarios by ensuring the VCCPT is powered up:
- PLL cascading and reconfiguration are supported.
- You may use any available regular I/O pins as clock input and clock output pins for this I/O bank I/O PLL.
If one of the sub-banks is not available in the HSIO bank, the fabric-feeding I/O PLL in this HSIO bank has only one pair of dedicated clock input pins which is from the available sub-bank. Reconfiguration is supported by this fabric-feeding I/O PLL.
Figure 9. Fabric-feeding I/O PLL location in HVIO Block