1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813667
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices 2. Getting Started 3. Functional Description 4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP 5. Interface Signals 6. Configuration Registers 7. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs Archives 8. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices x
1.1. Release Information 1.2. Features 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization
2. Getting Started x
2.1. Introduction to Intel® FPGA IP 2.2. Installing and Licensing Intel® FPGA IPs 2.3. Specifying the IP Core Parameters and Options 2.4. Generated File Structure 2.5. Simulating Intel® FPGA IPs 2.6. Integrating Your IP Core in Your Design
2.2. Installing and Licensing Intel® FPGA IPs x
2.2.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Adding the Agilex™ 5 Reference and System PLL IP
3. Functional Description x
3.1. Architecture 3.2. Clocking and Reset Sequence 3.3. Timing Constraints 3.4. Operation Speed Switching 3.5. USXGMII 3.6. Fmax Requirement
3.2. Clocking and Reset Sequence x
3.2.1. Clocking 3.2.2. Reset Sequence
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP x
4.1. Core Configuration 4.2. Analog Parameters
5. Interface Signals x
5.1. Clock Signals 5.2. Reset Signals 5.3. Serial Interface Signals 5.4. Avalon Memory-Mapped Interface Signals 5.5. XGMII Signals 5.6. GMII Signals 5.7. PHY Status Signals 5.8. Transceiver Mode and Operating Speed Signals 5.9. Transceiver Status and Reconfiguration Signals 5.10. GTS Reset Sequencer Signals 5.11. Dynamic Reconfiguration SRC Signals
6. Configuration Registers x
6.1. Register Map 6.2. PHY Registers
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices
2. Getting Started
3. Functional Description
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP
5. Interface Signals
6. Configuration Registers
7. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs Archives
8. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

4.1. Core Configuration

Table 14.   1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Core Parameters
Parameter Value Description
External PHY
Connect to MGBASE-T PHY On, Off Select this option when the external PHY is MGBASE compatible.

This parameter is enabled for 2.5G and 1G/2.5G (MGBASE) modes.
Connect to NBASE-T PHY

On, Off

Select this option when the external PHY is NBASE compatible.

This parameter is enabled for 10M/100M/1G/2.5G/5G/10G (USXGMII) modes.
PHY Options
Speed
  • 2.5G
  • 1G/2.5G
  • 1G/2.5G/10G
  • 10M/100M/1G/2.5G/5G/10G (USXGMII)
 The operating speed of the PHY.
Enable SGMII bridge On, Off Select this parameter to enable SGMII 10-Mbps/100-Mbps/1-Gbps.

You can enable this parameter for 1G/2.5G (MGBASE) mode.
Enable IEEE 1588 Precision Time Protocol On, Off

Select this parameter for the PHY to provide latency information to the MAC. The MAC requires this information if it enables the IEEE 1588v2 feature.

You can enable this parameter for 2.5G and 1G/2.5G (MGBASE).
Enable GMII8 Adapter On, Off Enable the 8-bit and 16-bit interface adapter at the MAC interface.
PCS Options
PHY ID (32 bit) 32-bit value

An optional 32-bit unique identifier:

  • Bits 3 to 24 of the Organizationally Unique Identifier (OUI) assigned by the IEEE
  • 6-bit model number
  • 4-bit revision number

The default value is 0x00000000.
Transceiver Options
Default transceiver mode

1G (MGBASE)

2.5G (MGBASE)

10G (MGBASE)

10G (NBASE) (USXGMII)

 Default transceiver mode during startup.
PMA reference frequency

156.250000

312.500000

322.265625

 Specify the frequency of the reference clock to PMA from i_clk_ref.

MGBASE supports 156.25 MHz and 312.5 MHz only. NBASE supports all three frequencies.
System PLL Frequency

322.2656 MHz

644.53125 MHz

 Specify the frequency of the System PLL clock. 322.2656 MHz frequency for MGBASE and 644.53125 MHz frequency for NBASE.
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