1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813667
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices 2. Getting Started 3. Functional Description 4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP 5. Interface Signals 6. Configuration Registers 7. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs Archives 8. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices x
1.1. Release Information 1.2. Features 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization
2. Getting Started x
2.1. Introduction to Intel® FPGA IP 2.2. Installing and Licensing Intel® FPGA IPs 2.3. Specifying the IP Core Parameters and Options 2.4. Generated File Structure 2.5. Simulating Intel® FPGA IPs 2.6. Integrating Your IP Core in Your Design
2.2. Installing and Licensing Intel® FPGA IPs x
2.2.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Adding the Agilex™ 5 Reference and System PLL IP
3. Functional Description x
3.1. Architecture 3.2. Clocking and Reset Sequence 3.3. Timing Constraints 3.4. Operation Speed Switching 3.5. USXGMII 3.6. Fmax Requirement
3.2. Clocking and Reset Sequence x
3.2.1. Clocking 3.2.2. Reset Sequence
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP x
4.1. Core Configuration 4.2. Analog Parameters
5. Interface Signals x
5.1. Clock Signals 5.2. Reset Signals 5.3. Serial Interface Signals 5.4. Avalon Memory-Mapped Interface Signals 5.5. XGMII Signals 5.6. GMII Signals 5.7. PHY Status Signals 5.8. Transceiver Mode and Operating Speed Signals 5.9. Transceiver Status and Reconfiguration Signals 5.10. GTS Reset Sequencer Signals 5.11. Dynamic Reconfiguration SRC Signals
6. Configuration Registers x
6.1. Register Map 6.2. PHY Registers
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices
2. Getting Started
3. Functional Description
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP
5. Interface Signals
6. Configuration Registers
7. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs Archives
8. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

5.7. PHY Status Signals

Table 21.  PHY Status Signals
Signal Name Direction Width Description PHY Configurations
led_char_err Output 1 Asserted when a 10-bit character error is detected for 1Gb or 2.5G.

This signal is not applicable for 10G.
  • 2.5G (MGBASE)
  • 1G/2.5G (MGBASE)
  • 10M/100M/1G/2.5G (MGBASE)
led_link Output 1 Asserted when the link synchronization for 1Gb or 2.5G is successful.

This signal is not applicable for 10G.
led_disp_err Output 1 Asserted when a 10-bit running disparity error is detected for 1Gb or 2.5G.

This signal is not applicable for 10G.
led_an Output 1 Asserted when auto-negotiation is completed.

This signal is not applicable for 10G.
  • 2.5G (MGBASE)
  • 1G/2.5G (MGBASE)
  • 10M/100M/1G/2.5G (MGBASE)
  • 10M/100M/1G/2.5G/5G/10G (USXGMII)
led_panel_link Output 1 When asserted, this signal indicates the following behavior:
Mode Behavior
1000 Base-X without auto-negotiation When asserted, indicates successful link synchronization.
SGMII mode without auto-negotiation When asserted, indicates successful link synchronization.
1000 Base-X with auto-negotiation Clause 37 Auto-negotiation status. The PCS function asserts this signal when auto-negotiation completes.
SGMII mode with MAC mode auto-negotiation Clause 37 Auto-negotiation status. The PCS function asserts this signal when auto-negotiation completes.
This signal is applicable only when SGMII 10M/100M mode is enabled.
  • 2.5G (MGBASE)
  • 1G/2.5G (MGBASE)
  • 10M/100M/1G/2.5G (MGBASE)
  • 10M/100M/1G/2.5G/5G/10G (USXGMII)
rx_block_lock Output 1 Asserted when the link synchronization for 10G of MGBASE and all speeds of USXGMII is successful.
  • 1G/2.5G/10G (MGBASE)
  • 10M/100M/1G/2.5G/10G (MGBASE)
  • 10M/100M/1G/2.5G/5G/10G (USXGMII)
tx_ready Output 1 Active high signal. When asserted, indicates that the TX datapath is ready to transmit data.
  • MGBASE variant
rx_ready Output 1 Active high signal. When asserted, indicates that the RX datapath is ready to receive data.
  • MGBASE variant
mrphy_pll_lock Output 1 Active high signal. When asserted, indicates that the PLL instantiated in the soft logic is locked to reference.
  • MGBASE variant (8-bit only)
o_tx_lanes_stable Output 1 Active-high asynchronous status signal for the TX datapath. Asserts when the TX datapath is ready to send data. Deasserts when the i_tx_rst_n or i_rst_n signal asserts. NBASE variant:
  • 10M/100M1G/2.5G/5G/10G (USXGMII)
o_rx_pcs_ready Output 1 Active-high asynchronous status signal for the RX datapath. Asserts when the RX datapath is ready to receive data. Deasserts when the i_rx_rst_n or i_rst_n signal asserts. NBASE variant:
  • 10M/100M1G/2.5G/5G/10G (USXGMII)
o_tx_pll_locked Output 1 Indicates that the TX serdes PLLs are locked. NBASE variant:
  • 10M/100M1G/2.5G/5G/10G (USXGMII)
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