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1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices
2. Getting Started
3. Functional Description
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP
5. Interface Signals
6. Configuration Registers
7. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs Archives
8. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
5.1. Clock Signals
5.2. Reset Signals
5.3. Serial Interface Signals
5.4. Avalon Memory-Mapped Interface Signals
5.5. XGMII Signals
5.6. GMII Signals
5.7. PHY Status Signals
5.8. Transceiver Mode and Operating Speed Signals
5.9. Transceiver Status and Reconfiguration Signals
5.10. GTS Reset Sequencer Signals
5.11. Dynamic Reconfiguration SRC Signals
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1.5. Resource Utilization
The following estimates are obtained by compiling the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 devices using the Quartus® Prime Pro Edition software.
Speed | ALM | ALUT | Logic Register | Memory Block (M20K) |
---|---|---|---|---|
10M/100M/1G/2.5G (with 8-bit/16-bit adapter for HPS) | 2725 | 2780 | 3746 | 4 |
10M/100M/1G/2.5G | 1204 | 1785 | 1805 | 2 |
1G/2.5G | 1442 | 1785 | 1812 | 2 |
10M/100M/1G/2.5G/5G/10G (USXGMII) | 1298 | 1797 | 2119 | 4 |