2024.10.07 |
24.3 |
4.0.0 |
- Removed the note about the Agilex™ 5 D-Series support in the About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices topic.
- Updated 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Core Features table.
- Updated Supported Line-side Modes for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices table.
- Updated Slowest Device Speed Grade Support table.
- Updated Resource Utilization table to add 10M/100M/1G/2.5G/5G/10G (MGBASE) and 1G/2.5G/10G (MGBASE) speed.
- Updated Generated IP Files table to add aldec and xcelium.
- Updated Architecture topic to update information about 2.5G, 1G/2.5G, 1G/2.5G/10G (MGBASE) and 10M/100M/1G/2.5G/5G/10G (USXGMII).
- Updated Architecture of the 2.5G, 1G/2.5G, 1G/2.5G/10G (MGBASE) Configuration figure.
- Updated Architecture of the 10M/100M/1G/2.5G/5G/10G (USXGMII) Configuration figure.
- Updated Clocking topic.
- Updated Clocking Specifications table.
- Updated figure title 2.5G, 1G/2.5G (MGBASE) Clocking to 2.5G, 1G/2.5G, 1G/2.5G/10G (MGBASE).
- Updated 2.5G, 1G/2.5G, 1G/2.5G/10G (MGBASE) Clocking figure.
- Updated 10M/100M/1G/2.5G/5G/10G (NBASE) Clocking figure.
- Updated Reset Sequence topic to add information about MGBASE and NBASE variants.
- Updated NBASE and MGBASE 10G Reset Block Diagram.
- Updated Timing Constraints table to include 1G/2.5G/10G (MGBASE) and 10M/100M/1G/2.5G/10G (MGBASE, SGMII) PHY configuration.
- Updated Operating Speed Switching Methodology table:
- Updated description for 1G/2.5G and 10M/100M/1G/2.5G PHY configuration.
- Added 1G/2.5G/10G (MGBASE) and 10M/100M/1G/2.5G/10G (MGBASE) PHY configuration.
- Updated Supported Operating Speed table to add information about 1G/2.5G/10G (MGBASE) and 10M/100M/1G/2.5G/10G (MGBASE).
- Updated Fmax Requirement table to include 10M/100M/1G/2.5G/10G (MGBASE) default rate (10G) variant.
- Updated 1G/2.5G/5G/10G Multirate Ethernet PHY Intel FPGA IP Core Parameters table to update the values for Speed parameter.
- Added a note in the Analog Parameters topic.
- Updated the PHY configurations and description columns in the Clock Signals table.
- Updated the PHY configurations columns in the Reset Signals table.
- Updated the signal names column in the Serial Interface Signals table.
- Updated the width and description columns in the Avalon Memory-Mapped Interface Signals table.
- Updated the width, description, and PHY configurations columns in the XGMII Signals table.
- Updated the PHY configurations column in the GMII Signals table.
- Updated the description and the PHY configurations columns in the PHY Status Signals table.
- Updated the description and the PHY configurations columns in the Transceiver Mode and Operating Speed Signals table.
- Updated the PHY configurations columns in the Dynamic Reconfiguration SRC Interface Signals table.
- Updated Register Map Overview table.
|
2024.07.08 |
24.2 |
3.0.0 |
- Added a note about Agilex™ 5 D-Series FPGAs and SoCs support in the About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices topic.
- Updated 1G/2.5G/5G/10G Multirate Ethernet PHY Interface with Agilex™ 5 Reference and System PLL Clocks IP figure in the Adding the Agilex 5 Reference and System PLL IP topic.
- Added Analog Parameter topic.
- Updated Interface Signals figure.
- Updated description for latency_sclk signal in Clock Signals table.
- Updated XGMII Signals table to add information about xgmii_tx_latency and xgmii_rx_latency signal.
- Updated PHY Registers table to include PTP registers information.
|
2024.04.01 |
24.1 |
2.1.0 |
Initial public release. |