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1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices
2. Getting Started
3. Functional Description
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP
5. Interface Signals
6. Configuration Registers
7. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs Archives
8. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
5.1. Clock Signals
5.2. Reset Signals
5.3. Serial Interface Signals
5.4. Avalon Memory-Mapped Interface Signals
5.5. XGMII Signals
5.6. GMII Signals
5.7. PHY Status Signals
5.8. Transceiver Mode and Operating Speed Signals
5.9. Transceiver Status and Reconfiguration Signals
5.10. GTS Reset Sequencer Signals
5.11. Dynamic Reconfiguration SRC Signals
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1.4. Device Speed Grade Support
Speed Mode | Slowest Supported Speed Grade | |
---|---|---|
With 1588 Feature | Without 1588 Feature | |
10M/100M/1G/2.5G/5G/10G (NBASE/USXGMII) | -I6, -E6 | -I6, -E6 |
1G/2.5G(MGBASE) (8-bit/16-bit) | -I6, -E6 | -I6, -E6 |
1G/2.5G/10G (MGBASE) | — | -I6, -E6 |
2.5G (MGBASE) (8-bit/16-bit) | -I6, -E6 | -I6, -E6 |