1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813667
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices 2. Getting Started 3. Functional Description 4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP 5. Interface Signals 6. Configuration Registers 7. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs Archives 8. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices x
1.1. Release Information 1.2. Features 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization
2. Getting Started x
2.1. Introduction to Intel® FPGA IP 2.2. Installing and Licensing Intel® FPGA IPs 2.3. Specifying the IP Core Parameters and Options 2.4. Generated File Structure 2.5. Simulating Intel® FPGA IPs 2.6. Integrating Your IP Core in Your Design
2.2. Installing and Licensing Intel® FPGA IPs x
2.2.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Adding the Agilex™ 5 Reference and System PLL IP
3. Functional Description x
3.1. Architecture 3.2. Clocking and Reset Sequence 3.3. Timing Constraints 3.4. Operation Speed Switching 3.5. USXGMII 3.6. Fmax Requirement
3.2. Clocking and Reset Sequence x
3.2.1. Clocking 3.2.2. Reset Sequence
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP x
4.1. Core Configuration 4.2. Analog Parameters
5. Interface Signals x
5.1. Clock Signals 5.2. Reset Signals 5.3. Serial Interface Signals 5.4. Avalon Memory-Mapped Interface Signals 5.5. XGMII Signals 5.6. GMII Signals 5.7. PHY Status Signals 5.8. Transceiver Mode and Operating Speed Signals 5.9. Transceiver Status and Reconfiguration Signals 5.10. GTS Reset Sequencer Signals 5.11. Dynamic Reconfiguration SRC Signals
6. Configuration Registers x
6.1. Register Map 6.2. PHY Registers
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices
2. Getting Started
3. Functional Description
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP
5. Interface Signals
6. Configuration Registers
7. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs Archives
8. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

3.2.1. Clocking

Clocking requirements:
  • tx_pll_refclk signal is the TX path reference clock for the PMA PLL. It is used to generate the serial clock and the parallel data clocks. Altera recommends that you use 156.25 MHz frequency for the tx_pll_refclk signal. Altera also recommends using the same clock for rx_cdr_refclk.
  • For 8-bit GMII (MGBASE):
    • The GMII 8-bit Adapter generates the gmii8b_tx_clkout clock signal. For 10M, the clock frequency is 2.5 MHz. For 100M (MII, 4-bit interface), the clock frequency is 25 MHz. For 1G and 2.5G (8-bit interface), the clock frequency is 125MHz and 312.5MHz respectively.
    • The hard processor system (HPS) ethernet media access controller (MAC) drives the gmii8b_tx_clkin signal at the same frequency with gmii8b_tx_clkout signal.
    • The refclk frequency for the MRPHY_PLL is 62.5MHz for 1G and 156.25 MHz for 2.5G.
  • For 16-bit GMII (MGBASE), transmit is clocked by tx_clkout. The PHY drives this clock to the MAC. The primary clock frequencies for 1G and 2.5G are 62.5 MHz and 156.25 MHz respectively. For 10M and 100M, the primary clock frequency is 62.5 MHz with clock enable.
  • xgmii_tx_coreclkin and xgmii_rx_coreclkin are available in MGBASE (10G) only.
  • For the USXGMII mode, the MAC drives the xgmii_tx_coreclkin to the PHY with a single clock frequency of 312.5 MHz.
Table 9.  Clocking Specifications
Clock Signals 10M (MII) 100M (MII) 1G (GMII) 2.5G 5G 10G
MGBASE (8-bit)

gmii8b_tx_clkin/gmii8b_tx_clkout

gmii8b_rx_clkin/gmii8b_rx_clkout

2.5 MHz

(4-bit interface)

 25 MHz

(4-bit interface)

 125 MHz

(8-bit interface)

 312.5 MHz

(8-bit interface)

 — —
MGBASE (16-bit)

tx_clkout

rx_clkout

62.5 MHz

(with clock enable)

 62.5 MHz

(with clock enable)

 62.5 MHz 156.25 MHz — —
MGBASE (64-bit)

xgmii_tx_coreclkin

xgmii_rx_coreclkin

— — — — — 156.25 MHz @ 64b
USXGMII (32-bit)

xgmii_tx_coreclkin

xgmii_rx_coreclkin

312.5 MHz

(with clock enable)

 312.5 MHz

(with clock enable)

 312.5 MHz

(with clock enable)

 312.5 MHz

(with clock enable)

 312.5 MHz

(with clock enable)

 312.5 MHz
Figure 8. 2.5G, 1G/2.5G, 1G/2.5G/10G (MGBASE) Clocking
Figure 9. 10M/100M/1G/2.5G/5G/10G (NBASE) Clocking
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