1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813667
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices 2. Getting Started 3. Functional Description 4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP 5. Interface Signals 6. Configuration Registers 7. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs Archives 8. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices x
1.1. Release Information 1.2. Features 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization
2. Getting Started x
2.1. Introduction to Intel® FPGA IP 2.2. Installing and Licensing Intel® FPGA IPs 2.3. Specifying the IP Core Parameters and Options 2.4. Generated File Structure 2.5. Simulating Intel® FPGA IPs 2.6. Integrating Your IP Core in Your Design
2.2. Installing and Licensing Intel® FPGA IPs x
2.2.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Adding the Agilex™ 5 Reference and System PLL IP
3. Functional Description x
3.1. Architecture 3.2. Clocking and Reset Sequence 3.3. Timing Constraints 3.4. Operation Speed Switching 3.5. USXGMII 3.6. Fmax Requirement
3.2. Clocking and Reset Sequence x
3.2.1. Clocking 3.2.2. Reset Sequence
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP x
4.1. Core Configuration 4.2. Analog Parameters
5. Interface Signals x
5.1. Clock Signals 5.2. Reset Signals 5.3. Serial Interface Signals 5.4. Avalon Memory-Mapped Interface Signals 5.5. XGMII Signals 5.6. GMII Signals 5.7. PHY Status Signals 5.8. Transceiver Mode and Operating Speed Signals 5.9. Transceiver Status and Reconfiguration Signals 5.10. GTS Reset Sequencer Signals 5.11. Dynamic Reconfiguration SRC Signals
6. Configuration Registers x
6.1. Register Map 6.2. PHY Registers
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices
2. Getting Started
3. Functional Description
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP
5. Interface Signals
6. Configuration Registers
7. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs Archives
8. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

5.2. Reset Signals

Table 16.   Reset Signals
Signal Name Direction Width Description PHY Configurations
reset Input 1 Active-high global reset. Assert this signal to trigger an asynchronous global reset. All MGBASE and NBASE variants
tx_digitalreset Input 1 Active-high signal. When asserted, triggers an asynchronous reset to the digital logic on the TX path and HSSI.
rx_digitalreset Input 1 Active-high signal. When asserted, triggers an asynchronous reset to the digital logic on the RX path and HSSI.
i_rst_n Input 1

Active-low asynchronous reset signal. Do not deassert until o_rst_ack_n asserts.

  • Resets the TX interface, including the TX PCS.
  • Resets the RX interface, including the RX PCS.
  • Resets the TX PMA and TX PLDIF.
  • Resets the RX PMA and RX PLDIF.

This reset leads to assertion of the o_rst_ack_n output signal.

o_rst_ack_n Output 1 Active-low asynchronous acknowledgment signal for the i_rst_n reset.

Do not deassert the i_rst_n reset until the o_rst_ack_n asserts.

i_tx_rst_n Input 1 Active-low asynchronous reset signal.

Resets the entire TX datapath, including the TX PCS, TX PMA, and TX PLDIF. Do not deassert until the o_tx_rst_ack_n asserts.

Note: In MGBASE mode, this reset impacts both TX and RX, as the TX clock is used in both direction.
o_tx_rst_ack_n Output 1 Active-low asynchronous acknowledgment signal for the i_tx_rst_n reset.

Do not deassert the i_tx_rst_n reset until o_tx_rst_ack_n asserts.

i_rx_rst_n Input 1 Active-low asynchronous reset signal.

Resets the entire RX datapath, including the RX PCS, RX PMA, and RX PLDIF. Do not deassert until o_rx_rst_ack_n asserts.

o_rx_rst_ack_n Output 1 Active-low asynchronous acknowledgment signal for the i_rx_rst_n reset.

Do not deassert the i_rx_rst_n reset until o_rx_rst_ack_n asserts.

gmii8b_tx_rst_n Input 1 Reset signal for the GMII8B adapter on the TX path.
gmii8b_rx_rst_n Input 1 Reset signal for the GMII8B adapter on the RX path.
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