Visible to Intel only — GUID: faf1663287718838
Ixiasoft
4.3.1.1. NOP(0x0)
4.3.1.2. get_hssi_profile for E-Tile
4.3.1.3. get_hssi_profile for F-Tile
4.3.1.4. set_hssi_profile for E-Tile
4.3.1.5. set_hssi_profile for F-Tile
4.3.1.6. read_MAC_statistic
4.3.1.7. get_mtu
4.3.1.8. set_csr for E-Tile
4.3.1.9. set_csr for F-Tile
4.3.1.10. get_csr for E-Tile
4.3.1.11. get_csr for F-Tile
4.3.1.12. enable_loopback for E-Tile
4.3.1.13. enable_loopback for F-Tile
4.3.1.14. disable_loopback for E-Tile
4.3.1.15. disable_loopback for F-Tile
4.3.1.16. Reset MAC Statistics
4.3.1.17. set_mtu for F-Tile
4.3.1.18. Ncsi_get_link_status
4.3.1.19. Reserved
4.3.1.20. firmware_version (0xFF)
6.1. Driving Multiple Ports with the Same Clock
6.2. Clock Connections for MAC Async Client FIFO
6.3. F-Tile Clock Connections for PTP Synchronous and Asynchronous cases
6.4. Clock Connections for SyncE Operation on E-Tile
6.5. Clock Connections for SyncE Operation on F-Tile
6.6. F-Tile PMA and FEC Direct PHY IP Clock Output
7.1.1. Device Feature Header Lo
7.1.2. Device Feature Header Hi
7.1.3. Feature GUID_L
7.1.4. Feature GUID_H
7.1.5. Feature CSR ADDR
7.1.6. Feature CSR Size Group
7.1.7. Version
7.1.8. Feature List
7.1.9. Interface Attribute Port X Parameters
7.1.10. HSSI Command/Status
7.1.11. HSSI Control/Address
7.1.12. HSSI Read Data
7.1.13. HSSI Write Data
7.1.14. HSSI Ethernet Port X Status
7.1.15. Priority Flow Control
7.1.16. Priority Flow Control TX Queue Statistics
7.1.17. Priority Flow Control RX Queue Statistics
7.1.18. Priority Flow Control TX Queue Threshold
7.1.19. Priority Flow Control RX Queue Threshold
7.1.20. F-Tile DR Controller Status
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Ixiasoft
8.4.3. Steps to Run the Design Example on Hardware
Running the design in hardware:
- Program the device via the JTAG programmer
- Open a System Console session
- Navigate to the hwtest_sl directory for E-tile designs or the hwtest_f directory for F-tile designs.
- Type source main_script.tcl
- Observe script output
The following sample output illustrates a successful hardware test run for the Ethernet Subsystem IP core design example on E-tile.
Available JTAG Masters: 0: /devices/10M16S(A|C|L)@2#USB-1#FM6 SI|SoC devkits#PG15SWIPLAB1062.gar.corp.intel.com/(link)/JTAG/(110:132 v1 #0)/phy_0/master 1: /devices/AGFB014R24A@1#USB-1#FM6 SI|SoC devkits#PG15SWIPLAB1062.gar.corp.intel.com/(link)/JTAG/alt_sld_fab_0_alt_sld_fab_0_sldfabric.node_0/hssi_ss_0_hssi_ss_dr_cpu_hssi_ss_dr_cpu_nios2_gen2_0.data_master 2: /devices/AGFB014R24A@1#USB-1#FM6 SI|SoC devkits#PG15SWIPLAB1062.gar.corp.intel.com/(link)/JTAG/alt_sld_fab_0_alt_sld_fab_0_sldfabric.node_3/phy_0/altera_jtag_avalon_master_0.master 3: /devices/AGFB014R24A@1#USB-1#FM6 SI|SoC devkits#PG15SWIPLAB1062.gar.corp.intel.com/(link)/JTAG/alt_sld_fab_0_alt_sld_fab_0_sldfabric.node_4/alt_sld_fab_0_alt_sld_fab_0_host_link_jtag.h2t/alt_sld_fab_0_alt_sld_fab_0_stfabric.h2t_0/alt_sld_fab_0_alt_sld_fab_0_memfabric_transacto.avalon_master Type set_jtag # to select a master Type list_jtag to display this list again Currently selected master is 1: /devices/AGFB014R24A@1#USB-1#FM6 SI|SoC devkits#PG15SWIPLAB1062.gar.corp.intel.com/(link)/JTAG/alt_sld_fab_0_alt_sld_fab_0_sldfabric.node_0/hssi_ss_0_hssi_ss_dr_cpu_hssi_ss_dr_cpu_nios2_gen2_0.data_master Info: (default) JTAG Port ID = 2 Info: (default) Internal Serial Loopback = 1 Info: (default) Port List = 0 4 8 12 Info: (default) PTP Enable = 0 0 0 0 Info: (default) EnhancedPTPAccuracy Enable = 0 1 0 0 Info: (default) Speed = 100G_fec 100G_fec 100G_fec 100G Info: (default) PCS Enabled List = 0 0 0 0 Info: (default) DR Enabled List = 0 0 0 0 Info: (default) Base Profile List = 0 0 0 0 Info: (default) Latency Measurement Enable = 0 Info: (default) Throughput Measurement Enable = 0 Info: (default) 100G PAM4 Enabled List = 1 1 1 1 Info: (default) PMA Adaptation = 0 0 0 0 Info: (default) PMAConfig Number (default) = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Info: Hotplug Enable (enable=1, disable=0) (default) : set hotplug_en 0 Info: PMA Calibration (enable=1, disable=0) (default) : set pma_calibration_en 1 ANLT Port 0 REG: 0x00000000 & anlt_en: 0 Info: Enabled internal loopback with calibration Info: Test <p0 c3_ehip_xcvr_loopback_test> Passed Info: Test <p0 c3_ehip_traffic_basic_test> Passed ANLT Port 4 REG: 0x00000000 & anlt_en: 0 Info: Enabled internal loopback with calibration Info: Test <p4 c3_ehip_xcvr_loopback_test> Passed Info: Test <p4 c3_ehip_traffic_basic_test> Passed ANLT Port 8 REG: 0x00000000 & anlt_en: 0 Info: Enabled internal loopback with calibration Info: Test <p8 c3_ehip_xcvr_loopback_test> Passed Info: Test <p8 c3_ehip_traffic_basic_test> Passed ANLT Port 12 REG: 0x00000000 & anlt_en: 0 Info: Enabled internal loopback with calibration Info: Test <p12 c3_ehip_xcvr_loopback_test> Passed Info: Test <p12 c3_ehip_traffic_basic_test> Passed