Ethernet Subsystem Intel® FPGA IP User Guide

ID 773413
Date 12/08/2023
Public

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6.2. Clock Connections for MAC Async Client FIFO

When "Enable asynchronous adapter clocks" is set to Enable (for E- and F- tile) and "Client Interface" is set to MAC Avalon ST (for F-tile) in the IP GUI, p<n>_app_ss_st_rx_clk and p<n>_app_ss_st_tx_clk can be asynchronous from each other and from o_p<n>_clk_pll. The only requirement on the clocks is that they be fast enough so that no data will be dropped by the port. No additional async FIFO or special data valid sequence is required in soft logic to use this mode.

Figure 11. Clock Connections for MAC+PCS Async Operation

The Tile Refclk/PLL IP and i_clk_sys is instantiated within HSSI SS and only applicable for F-tile.

Table 44.  Minimum Clock Rates for MAC Client Async FIFO Operation, Assuming 12 byte IPGThe following table shows the minimum rates required. Note that the 100G rate is lower because the MAC interface is 512b wide.
Rate Min p<n>_app_ss_st_tx_clk Min p<n>_app_ss_st_rx_clk
10G 156.25 MHz

o_p<n>_clk_rec_div or

156.25 +200 ppm for F-tile or 100 ppm for E-tile

25G/50G 390.625 MHz

o_p<n>_clk_rec_div or

390.625 MHz +200 ppm for F-tile or 100 ppm for E-tile

40G 312.5 MHz 312.5 +200 ppm for F-tile or 100 ppm for E-tile
100G

F-tile:

380 MHz (Preamble Passthrough Enabled)

340 MHz (Preamble Passthrough Disabled)

E-tile:

280.90 MHz (Preamble Passthrough Enabled)

240 MHz (Preamble Passthrough Disabled)

F-tile:

380 MHz (Preamble Passthrough Enabled)

340 MHz (Preamble Passthrough Disabled)

E-tile:

280.90 MHz +100 ppm

240 MHz