Visible to Intel only — GUID: qyq1663300473439
Ixiasoft
4.3.1.1. NOP(0x0)
4.3.1.2. get_hssi_profile for E-Tile
4.3.1.3. get_hssi_profile for F-Tile
4.3.1.4. set_hssi_profile for E-Tile
4.3.1.5. set_hssi_profile for F-Tile
4.3.1.6. read_MAC_statistic
4.3.1.7. get_mtu
4.3.1.8. set_csr for E-Tile
4.3.1.9. set_csr for F-Tile
4.3.1.10. get_csr for E-Tile
4.3.1.11. get_csr for F-Tile
4.3.1.12. enable_loopback for E-Tile
4.3.1.13. enable_loopback for F-Tile
4.3.1.14. disable_loopback for E-Tile
4.3.1.15. disable_loopback for F-Tile
4.3.1.16. Reset MAC Statistics
4.3.1.17. set_mtu for F-Tile
4.3.1.18. Ncsi_get_link_status
4.3.1.19. Reserved
4.3.1.20. firmware_version (0xFF)
6.1. Driving Multiple Ports with the Same Clock
6.2. Clock Connections for MAC Async Client FIFO
6.3. F-Tile Clock Connections for PTP Synchronous and Asynchronous cases
6.4. Clock Connections for SyncE Operation on E-Tile
6.5. Clock Connections for SyncE Operation on F-Tile
6.6. F-Tile PMA and FEC Direct PHY IP Clock Output
7.1.1. Device Feature Header Lo
7.1.2. Device Feature Header Hi
7.1.3. Feature GUID_L
7.1.4. Feature GUID_H
7.1.5. Feature CSR ADDR
7.1.6. Feature CSR Size Group
7.1.7. Version
7.1.8. Feature List
7.1.9. Interface Attribute Port X Parameters
7.1.10. HSSI Command/Status
7.1.11. HSSI Control/Address
7.1.12. HSSI Read Data
7.1.13. HSSI Write Data
7.1.14. HSSI Ethernet Port X Status
7.1.15. Priority Flow Control
7.1.16. Priority Flow Control TX Queue Statistics
7.1.17. Priority Flow Control RX Queue Statistics
7.1.18. Priority Flow Control TX Queue Threshold
7.1.19. Priority Flow Control RX Queue Threshold
7.1.20. F-Tile DR Controller Status
Visible to Intel only — GUID: qyq1663300473439
Ixiasoft
5.1.3. AXI-ST PHY Direct
The AXI-ST PHY Direct Interface is available when user select below profiles as Subsystem Profiles for specific port.
Ethernet PMA/FEC/PCS-Direct, MII, General PMA/FEC/PCS-Direct, OTN, Flex-E, TSE PCS
Please refer to AXI-ST Client Interface section for detail on the existence of AXI-ST PHY Direct and AXI-ST Client interface when DR Extension Subsystem is enabled.
Signal Name | Direction | Type | Description |
---|---|---|---|
p{0..NUM_PORT}_app_ss_st_txphydirect_clk | In | Clock | The TX clock for the IP core that drives the channel. |
p{0..NUM_PORT}_app_ss_st_ txphydirect_areset_n[PORTX_CHANNEL-1:0] | In | Reset | Asynchronous reset. |
p{0..NUM_PORT}_app_ss_st_ txphydirect_tdata[PORTX_CHANNEL-1:0][ PORTX_DATA_WIDTH-1:0] | In | Data | Tx PHY Direct parallel data |
p{0..NUM_PORT}_ss_app_st_ txphydirect_tready [PORTX_CHANNEL-1:0] | Out | Status | Ready signal for PHY Direct data |
p{0..NUM_PORT}_app_ss_st_ txphydirect_tvalid [PORTX_CHANNEL-1:0] | In | Status | Valid signal for PHY Direct data |
Signal Name | Direction | Type | Description |
---|---|---|---|
p{0..NUM_PORT}_app_ss_st_rxphydirect _clk | In | Clock | The RX clock for the IP core that drives the channel. |
p{0..NUM_PORT}_app_ss_st_ rxphydirect_areset_n[PORTX_CHANNEL-1:0] | In | Reset | Asynchronous reset. |
p{0..NUM_PORT}_ss_app_st_ rxphydirect_tdata[PORTX_CHANNEL-1:0][PORTX_DATA_WIDTH-1:0] | Out | Data | Rx PHY Direct parallel data. |
p{0..NUM_PORT}_ss_app_st_ rxphydirect_tvalid | Out | Status | Valid signal for PHY Direct data. |