Ethernet Subsystem Intel® FPGA IP User Guide

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ID 773413
Date 12/08/2023
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Feature Description 3. Ethernet Subsystem Parameters 4. Subsystem IP Blocks 5. Interfaces and Signals 6. Recommended Clock Connections 7. Register Descriptions 8. Ethernet SS IP Example Design 9. Document Revision History for the Ethernet Subsystem Intel FPGA IP User Guide
1. Introduction x
1.1. Supported Features 1.2. Device Family Support 1.3. Release Information 1.4. Resource Utilization 1.5. Getting Started
2. Feature Description x
2.1. Ethernet Subsystem Intel FPGA IP Overview 2.2. Supported Features
3. Ethernet Subsystem Parameters x
3.1. Parameter Editor Parameters 3.2. E-Tile Port Enablement Guidelines and Restrictions 3.3. F-Tile Ethernet Port to PMA Channel Mapping
4. Subsystem IP Blocks x
4.1. AXI Stream Bridge 4.2. CSR Address Decoder 4.3. Subsystem Abstraction Layer (SAL) 4.4. Dynamic Reconfiguration Extension Subsystem 4.5. IEEE 1588v2 PTP 4.6. Auto-Negotation and Link Training 4.7. Priority Flow Control
4.3. Subsystem Abstraction Layer (SAL) x
4.3.1. Subsystem Abstraction Layer (SAL) Commands
4.3.1. Subsystem Abstraction Layer (SAL) Commands x
4.3.1.1. NOP(0x0) 4.3.1.2. get_hssi_profile for E-Tile 4.3.1.3. get_hssi_profile for F-Tile 4.3.1.4. set_hssi_profile for E-Tile 4.3.1.5. set_hssi_profile for F-Tile 4.3.1.6. read_MAC_statistic 4.3.1.7. get_mtu 4.3.1.8. set_csr for E-Tile 4.3.1.9. set_csr for F-Tile 4.3.1.10. get_csr for E-Tile 4.3.1.11. get_csr for F-Tile 4.3.1.12. enable_loopback for E-Tile 4.3.1.13. enable_loopback for F-Tile 4.3.1.14. disable_loopback for E-Tile 4.3.1.15. disable_loopback for F-Tile 4.3.1.16. Reset MAC Statistics 4.3.1.17. set_mtu for F-Tile 4.3.1.18. Ncsi_get_link_status 4.3.1.19. Reserved 4.3.1.20. firmware_version (0xFF)
4.5. IEEE 1588v2 PTP x
4.5.1. TX PTP Classifier
5. Interfaces and Signals x
5.1. AXI4 Interfaces 5.2. Serial Interface 5.3. Clocks 5.4. Resets
5.1. AXI4 Interfaces x
5.1.1. AXI-Lite CSR 5.1.2. AXI-ST Client Interface 5.1.3. AXI-ST PHY Direct 5.1.4. AXI-ST PTP 5.1.5. Flow Control
6. Recommended Clock Connections x
6.1. Driving Multiple Ports with the Same Clock 6.2. Clock Connections for MAC Async Client FIFO 6.3. F-Tile Clock Connections for PTP Synchronous and Asynchronous cases 6.4. Clock Connections for SyncE Operation on E-Tile 6.5. Clock Connections for SyncE Operation on F-Tile 6.6. F-Tile PMA and FEC Direct PHY IP Clock Output
7. Register Descriptions x
7.1. Subsystem Registers 7.2. Port Registers 7.3. F-Tile Address Maps 7.4. F-Tile ANLT Port Register Map 7.5. F-Tile PTP Tile Adapter Register Map 7.6. F-Tile DR Controller Register Map
7.1. Subsystem Registers x
7.1.1. Device Feature Header Lo 7.1.2. Device Feature Header Hi 7.1.3. Feature GUID_L 7.1.4. Feature GUID_H 7.1.5. Feature CSR ADDR 7.1.6. Feature CSR Size Group 7.1.7. Version 7.1.8. Feature List 7.1.9. Interface Attribute Port X Parameters 7.1.10. HSSI Command/Status 7.1.11. HSSI Control/Address 7.1.12. HSSI Read Data 7.1.13. HSSI Write Data 7.1.14. HSSI Ethernet Port X Status 7.1.15. Priority Flow Control 7.1.16. Priority Flow Control TX Queue Statistics 7.1.17. Priority Flow Control RX Queue Statistics 7.1.18. Priority Flow Control TX Queue Threshold 7.1.19. Priority Flow Control RX Queue Threshold 7.1.20. F-Tile DR Controller Status
7.2. Port Registers x
7.2.1. PTP Packet Classifier Registers
7.2.1. PTP Packet Classifier Registers x
7.2.1.1. Recognized and Unrecognized Packet Counters 7.2.1.2. Parse Graph Specific Packet Counters
8. Ethernet SS IP Example Design x
8.1. Steps to Generate the Example Design 8.2. Supported Simulators 8.3. Running the Simulation Tests 8.4. Running the Hardware Tests
8.3. Running the Simulation Tests x
8.3.1. Steps to Simulate the Design Example
8.4. Running the Hardware Tests x
8.4.1. Supported Boards 8.4.2. Steps to Compile the Design Example for Hardware 8.4.3. Steps to Run the Design Example on Hardware
8.4.2. Steps to Compile the Design Example for Hardware x
8.4.2.1. Steps to generate Routing Delay for PTP Enabled Designs
1. Introduction
2. Feature Description
3. Ethernet Subsystem Parameters
4. Subsystem IP Blocks
5. Interfaces and Signals
6. Recommended Clock Connections
7. Register Descriptions
8. Ethernet SS IP Example Design
9. Document Revision History for the Ethernet Subsystem Intel FPGA IP User Guide

5.1.2. AXI-ST Client Interface

All AXI-ST Tx interface clocks are synchronous to p<n>_app_ss_st_tx_clk while all AXI-ST Rx interface clock is synchronous to p<n>_app_ss_st_rx_clk. The resets for AXI-ST Tx/Rx interfaces are p<n>_app_ss_st_tx_areset_n and p<n>_app_ss_st_rx_areset_n. The interface is compliant to the AXI Standard.

When the DR Extension Subsystem is enabled, both AXI-ST Client and AXI-ST PHY Direct interface are available for same port. This will allow the switching between protocols, for example, 25G Ethernet protocol using 25GbE profile will use AXI-ST Client and when DR for same port happen to CPRI protocol, the datapath will switch to AXI-ST PHY Direct interface.

Note: The AXI-ST Client interface is compliant with AXI-ST Specifications. However, AXI-ST Client interface tvalid signal is not allowed to de-assert in the middle of packet transmission when tready is asserted, else underflow could occur, and the MAC TX inserts an error character |E| into the frame.
Table 29.  AXI-ST TX Client Interface SignalsThe following table shows the AXI4-ST TX interface signals.
Signal Name Direction Description
p<n>_app_ss_st_tx_clk In Clock signal of each enabled port.
p<n>_app_ss_st_tx_areset_n In Asynchronous reset of each enabled port
p<n>_app_ss_st_tx_tvalid In

When asserted, the TX data signal is valid.

This signal must be continuously asserted between the assertions of the start of packet and end of packet signals for the same packet; except when tready is deasserted.

p<n>_ss_app_st_tx_tready Out Txready signal.
p<n>_app_ss_st_tx_tdata [PORTX_DATA_WIDTH-1:0] In

Data signals.

400GE Profile:

PORTX_DATA_WIDTH=1024

200GE Profile:

PORTX_DATA_WIDTH=512

100GE Profile:

PORTX_DATA_WIDTH= 256

40GE/50GE Profile:

PORTX_DATA_WIDTH=128

10GE/25GE Profile: PORTX_DATA_WIDTH= 64
p<n>_app_ss_st_tx_tkeep [PORTX_DATA_WIDTH/8-1:0] In 1'b1 for data byte.1'b0 for null byte.
Note: Null byte is not allowed in the beginning or then middle of a transfer. A null byte is only applicable during end of transfer.

400GE Profile:

PORTX_DATA_WIDTH=1024

200GE Profile:

PORTX_DATA_WIDTH=512

100GE Profile:

PORTX_DATA_WIDTH= 256

40GE/50GE Profile: PORTX_DATA_WIDTH= 128

10GE/25GE Profile: PORTX_DATA_WIDTH = 64
p<n>_app_ss_st_tx_tlast In Indicates the end of the transfer.
p<n>_app_ss_st_tx_tuser_client[1:0] - 25GeE, 10GbE

[3:0] - 40GCAUI-4, 50GAUI-2, 50GAUI-1

[7:0] - 100GCAUI-4, 100GAUI-2, 100GAUI-1

[15:0] 200GAUI-4, 200GAUI-2

[31:0] 400GAUI-8, 400GAUI-4

 In

TxClient User signal. Segment 0 (Repeated for each available segment based on profile):

[1] - Driving “0” on this port means TX MAC will add CRC and “1” means MAC will not add CRC i.e. no PAD and no source address insertion.Please note i_tx_skip_crc needs to be held to the selected value (1 or 0) for the whole packet. For PTP 1-step packet, i_tx_skip_crc must be 0.

[0] - When asserted in an EOP cycle (while the EOP signal is asserted), directs the IP core to insert an error in the packet before sending it on the Ethernet link.

p<n>_app_ss_st_tx_tuser_ptp[93:0] In

TxPTP User signal.

Applicable when Ethernet rate is 400G (F-tile only), tie to 0 for other rate:

[93:92] – Clock Mode of incoming PTP Tx packet (i_clock_type).

2'b00: Ordinary Clock

2'b01: Boundary Clock

2'b10: End-to-end Transparent Clock

2'b11: Peer-to-peer Transparent Clock

[91:61] - Fingerprint for current TX Packet (i_ptp_fp[31:0], MSB tie to 0 if fingerprint width is less than 32)

[59:59] - Add peer-to-peer mean path delay to correction field for current TX packet (i_ptp_p2p[1])

[58:58] - Add asymmetry to correction field for current TX packet (i_ptp_asym[1])

[57:57] - Sign of asymmetry delay add to correction field for current TX packet (i_ptp_asym_sign[1])

[56:50] - Index of asymmetry delay and peer-to-peer mean path delay in the configurable lookup table (i_ptp_asym_p2p_idx[13:7])

[49:49] - Insert an Egress Timestamp into the current TX Packet (i_ptp_ins_ets[1]), internally generated when packet classifier instantiated within HSSI SS.

[48:48] - Request a 2-step timestamp for the current TX packet (i_ptp_ts_req[1])

Applicable when Ethernet rate is 10G/25G/50G/100G/200G:

[47:46] – Clock Mode of incoming PTP Tx packet (i_clock_type).

[45:14] - Fingerprint for current TXPacket (i_ptp_fp[31:0], MSB tie to 0 if fingerprint width is less than 32).

[13:13]- Add peer-to-peer mean path delay to correction field for current TX packet (i_ptp_p2p[0], Exist on F-tile only)

[12:12] - Add asymmetry to correction field for current TX packet(i_ptp_asym[0], Exist on F tile only)

[11:11]- Sign of asymmetry delay add to correction field for current TX packet (i_ptp_asym_sign[0], Exist on F-tile only)

[10:4]- Index of asymmetry delay and peer-to-peer mean path delay in the configurable lookup table (i_ptp_asym_p2p_idx[6:0], Exist on F-tile only)

[3:3]- Insert an Egress Timestamp into the current TX Packet (i_ptp_ins_ets[0]),

internally generated when packet classifier instantiated within HSSI SS.

[2:2] - Request a 2-step timestamp for the current TX packet (i_ptp_ts_req[0])

[1:1]- Indicate PTP fields in tx_tuser_ptp[93:48] is valid when Ethernet rate is 400G (F-tile only), used to determine whether to fold the tx_tuser_ptp[93:48] into NOC (No usage within HSSI SS, mainly use for NOC)

[0:0] -

Indicate PTP fields in tx_tuser_ptp[47:2] is valid when Ethernet rate is 10G/25G/40G/50G/100G/200G/400G, used to determine whether to fold the tx_tuser_ptp[47:2] into NOC (No usage within HSSI SS, mainly use for NOC)
p<n>_app_ss_st_tx_tuser_ptp_extended [327:0] In

TxPTP User Extended signal.

Applicable when Ethernet rate is 400G (F-tile only), tie to 0 for other rates:

[327:312] - Timestamp offset, internally generated when packet classifier instantiated within HSSI SS.

[311:296] - Correction Field offset, internally generated when packet classifier instantiated within HSSI SS.

[295:280] - Checksum offset, internally generated when packet classifier instantiated within HSSI SS.

[279:264] - Extended Byte offset, internally generated when packet classifier instantiated within HSSI SS.

[263:263] - Zero Checksum, internally generated when packet classifier instantiated within HSSI SS.

[262:262] - Update Extended Byte, internally generated when packet classifier instantiated within HSSI SS.

[261:261] - Timestamp Format, internally generated when packet classifier instantiated within HSSI SS.

[260:165] - Ingress Timestamp for TX Packet Residence Time Calculation (i_ptp_tx_its[191:96])

[164:164] - Update correction field with residence time in the current TX packet (i_ptp_ins_cf[1]), internally generated when packet classifier instantiated within HSSI SS.

Applicable when Ethernet rate is 10G/25G/50G/100G/200G/400G:

[163:148] - Timestamp offset, internally generated when packet classifier instantiated within the ethernet subsystem.

[147:132] - Correction Field offset, internally generated when packet classifier instantiated within the ethernet subsystem.

[131:116] - Checksum offset, internally generated when packet classifier instantiated within the ethernet subsystem.

[115:100]- Extended Byte offset, internally generated when packet classifier instantiated within the ethernet subsystem.

[99:99] - Zero Checksum, internally generated when packet classifier instantiated within the ethernet subsystem.

[98:98]- Update Extended Byte, internally generated when packet classifier instantiated within the ethernet subsystem.

[97:97] - Timestamp Format, internally generated when packet classifier instantiated within the ethernet subsystem.

[96:1]- Ingress Timestamp for TX Packet Residence Time Calculation.

[0:0]- Update correction field with residence time in the current TX packet, internally generated when packet classifier instantiated within the ethernet subsystem.

Not applicable for 40G variant.
Table 30.  AXI-ST RX Client Interface SignalsThe following table shows the AXI4-ST RX interface signals.
Signal Name Direction Description
p<n>_app_ss_st_rx_clk In Clock signal of each enabled port.
p<n>_app_ss_st_rx_areset_n In Asynchronous reset of each enabled port.
p<n>_ss_app_st_rx_tvalid Out Data valid signal of each enabled port.
p<n>_ss_app_st_rx_tdata [PORTX_DATA_WIDTH-1:0] Out Data bus of each enabled port.
p<n>_ss_app_st_rx_tkeep [PORTX_DATA_WIDTH-1:0] Out
  • 1'b1 for data byte.
  • 1'b0for null byte.
Note: Null byte is not allowed in the beginning or the middle of transfer, it is only applicable during end of transfer.
p<n>_ss_app_st_rx_tlast Out Indicates the end of a transfer.
p<n>_ss_app_st_rx_tuser_client[6:0] - 25GbE, 10GbE

[13:0] 40GCAUI-4, 50GCAUI-2, 50GAUI-1

[20:0] 100GCAUI-4, 100GAUI-2, 100GAUI-1

[27:0] 200GAUI-4, 200GAUI-2

[34:0] 400GAUI-8, 400GAUI-4

 Out

Rx Packet Error Status.

Segment 0 (Repeated for each available segment based on profile):

[6]-PHY error.

[5]-CRC error.

[4]- Length error: Frame advertised a payload that was a valid length, but longer than the payload that actually arrived.

[3]-Oversize error.

[2]-Undersized (frame shorter than 64b) or oversized (frame larger than the programmed max_frame_size).

[1]-FCS error.

[0]-Malformed

(terminated with a control block other than Term).
p<n>_ss_app_st_rx_tuser_sts[4:0]-25GbE, 10GbE

[9:0] 40GCAUI-4, 50GCAUI-2, 50GAUI-1

[14:0] 100GCAUI-4, 100GAUI-2, 100GAUI-1

[19:0] 200GAUI-4, 200GAUI-2

[24:0] 400GAUI-8, 400GAUI-4

 Out

Rx Packet Status. [4:0]:

Segment 0 (Repeated for each available segment based on profile):

4'b0000- Had a valid length (was a data frame).

4'b0001- Ethernet type that was not FC (not applicable for E-tile).

4'b0010- Broadcast or Multicast frame (not applicable for E-tile).

4'b0011- PTP frame.

(Length/Type= 0x88F7) (not applicable for E-tile).

4'b0100 - SFC/PFC frame.

4'b0101- SVLAN/VLAN frame.

4'b0110- Illegal length type. 4'b0111- FC frame (control frame, but not SFC/PFC/Pause frame).

4'b1000 - reserved

4'b1001- Pause frame (not applicable for E-tile).
p<n>_ss_app_st_rx_tuser_sts_extended[31:0] Out

Rx Packet Extended Status.

  • bits [31:16]: Specifies the frame length from the first byte of the destination address to the last byte of the FCS.
  • bits[15:0]: Specifies the payload length.
p<n>_ss_app_st_rx_tuser_pkt_seg_parity [PORT_DATA_WIDTH/64-1:0] Out

Packet Segment Parity:

Provides odd parity protection for the segments of the packets. This bit is valid on every packet segment transfer. There can be one or more packet segment parity bits per transfer clock, each protecting its own segments for multi-segment packet for that transfer clock.

p<n>_ss_app_st_rx_tuser_last_segment<segment number> Out Packet segmentation boundary indication for higher bandwidth transfer. Last_segment is bit-blasted signal. For example, with NUM_OF_SEG being 2:

p0_ss_app_st_rx_tuser_last_segment0,

p0_ss_app_st_rx_tuser_last_segment1

Exists in F-tile and when MAC segmented interface protocol is enabled.
p<n>_ss_app_st_rx_tuser_last_buf_pkt_truncation<segment number> Out Packet truncation indication: Indicates whether the packet is erroneous and truncated at the end of packet. Available only when Enable SFC/PFC Queue Buffering parameter is enabled.
Figure 8. Overall View of Transactions on the AXI-4 Streaming RX Interface
Level Two Title