Visible to Intel only — GUID: mkm1663373489183
Ixiasoft
4.3.1.1. NOP(0x0)
4.3.1.2. get_hssi_profile for E-Tile
4.3.1.3. get_hssi_profile for F-Tile
4.3.1.4. set_hssi_profile for E-Tile
4.3.1.5. set_hssi_profile for F-Tile
4.3.1.6. read_MAC_statistic
4.3.1.7. get_mtu
4.3.1.8. set_csr for E-Tile
4.3.1.9. set_csr for F-Tile
4.3.1.10. get_csr for E-Tile
4.3.1.11. get_csr for F-Tile
4.3.1.12. enable_loopback for E-Tile
4.3.1.13. enable_loopback for F-Tile
4.3.1.14. disable_loopback for E-Tile
4.3.1.15. disable_loopback for F-Tile
4.3.1.16. Reset MAC Statistics
4.3.1.17. set_mtu for F-Tile
4.3.1.18. Ncsi_get_link_status
4.3.1.19. Reserved
4.3.1.20. firmware_version (0xFF)
6.1. Driving Multiple Ports with the Same Clock
6.2. Clock Connections for MAC Async Client FIFO
6.3. F-Tile Clock Connections for PTP Synchronous and Asynchronous cases
6.4. Clock Connections for SyncE Operation on E-Tile
6.5. Clock Connections for SyncE Operation on F-Tile
6.6. F-Tile PMA and FEC Direct PHY IP Clock Output
7.1.1. Device Feature Header Lo
7.1.2. Device Feature Header Hi
7.1.3. Feature GUID_L
7.1.4. Feature GUID_H
7.1.5. Feature CSR ADDR
7.1.6. Feature CSR Size Group
7.1.7. Version
7.1.8. Feature List
7.1.9. Interface Attribute Port X Parameters
7.1.10. HSSI Command/Status
7.1.11. HSSI Control/Address
7.1.12. HSSI Read Data
7.1.13. HSSI Write Data
7.1.14. HSSI Ethernet Port X Status
7.1.15. Priority Flow Control
7.1.16. Priority Flow Control TX Queue Statistics
7.1.17. Priority Flow Control RX Queue Statistics
7.1.18. Priority Flow Control TX Queue Threshold
7.1.19. Priority Flow Control RX Queue Threshold
7.1.20. F-Tile DR Controller Status
Visible to Intel only — GUID: mkm1663373489183
Ixiasoft
6.1. Driving Multiple Ports with the Same Clock
The figure in Recommended Clock Connections for Normal Operation in Recommended Clock Connections is simple and functions correctly, however, it is better to share a single clock between multiple ports.
Figure 10. Sharing o_p<n>_clk_pll
It is possible to share the same clock source between multiple Ethernet ports as long as the following conditions are met:
- The shared clock can be traced to a common source reference clock. You must note that any clock source that derives the correct clock frequency from the same source clock as the port’s i_ref_clk can be used to drive the datapath clocks. Here are a few examples of alternative clock sources.
- o_p<n>_clk_pll or its equivalent from an unrelated transceiver tile that is connected to the same reference clock source, and whose system clock is configured to the same rate (For F-tile).
- An IO PLL or FPLL in fabric that derives its refclk from the same reference clock source.
- A GPIO directly connected to the reference clock, providing a 161.1328125 MHz clock to a port that can use p<n>_app_ss_st_tx_clk/p<n>_app_ss_st_rx_clk running at that speed.
The Tile Refclk/PLL IP and i_clk_sys are instantiated within HSSI SS and only applicable for F-tile.