Ethernet Subsystem Intel® FPGA IP User Guide

ID 773413
Date 12/08/2023
Public

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Document Table of Contents

9. Document Revision History for the Ethernet Subsystem Intel FPGA IP User Guide

Document Version Intel® Quartus® Prime Version Changes
2023.12.08 23.4 Made the following changes:
  • Updated disclaimer statement in Introduction.
  • Updated Resource Utilization table for E-Tile and F-Tile in Resource Utilization.
  • Added the new IP parameter: Enable SFE/PFC Queue Buffering in Ethernet Subsystem Intel FPGA IP Parameters.
  • Added new topic: Priority Flow Control.
  • Updated Flow Control Signals table in Flow Control.
  • Added QuestaSim* (VHDL/Verilog) (Excluding QuestaSim FPGA Edition) in Supported Simulators.
  • Corrected Enable ECC Protection description in Ethernet Subsystem Intel FPGA IP Parameters: HSSI.
  • Added new IP parameter: Enable System PLL for F-Tile in Ethernet Subsystem Intel FPGA IP Parameters: HSSI.
  • Added AXI configuration in Ethernet Subsystem - IP Configuration Tab.
  • Corrected the 40G/50G speed in AXI Stream Bridge table and added a note stating that the F-Tile system PLL IP is integrated when Enable System PLL for F-Tile parameter is turned ON.
  • Corrected the AN/LT section description in Auto-Negotation and Link Training.
  • Added a new row p<n>_ss_app_st_rx_tuser_tlast_buf_pkt_truncation<segment number> to the AXI-ST RX Client Interface Signals table in AXI-ST Client Interface.
  • Updated Flow Control Signals section.
  • Added a new table Reset Signals-Block level in Resets.
  • Added the following new sections in Subsystem Registers of Register Description section.
    • Priority Flow Control TX Queue Statistics
    • Priority Flow Control RX Queue Statistics
    • Priority Flow Control TX Queue Threshold
    • Priority Flow Control RX Queue Threshold
    • F-Tile DR Controller Status
  • Updated table F-Tile Register Map for Port Enabled with Ethernet Protocol table in F-Tile Address Maps.
  • Removed F-Tile Register Map for per-channel Transceiver Reconfiguration Interface.
  • Added a new section F-Tile DR Controller Register Map.
2023.10.02 23.3 Made the following changes:
  • Updated register description table for bits[4:1] for E-Tile in Ncsi_get_link_status.
  • Updated Dynamic Reconfiguration Extension Subsystem section.
  • Updated resource utilization table for F-Tile in Resource Utilization.
2023.08.29 23.2
  • Updated Ethernet Subsystem Intel FPGA IP Features table in Supported Features section.
    • 200GbE GAUI-8 for F-Tile device.
  • Added Device Family Support section.
  • Updated Release Information section.
  • Added 200GbE GAUI-4/200GbE GAUI-8 port in Feature Description.
  • Updated Supported Ethernet Features table in Supported Features.
  • Added Enable ECC protection parameter in General Configuration tab.
  • Added the following parameters in Port_<port_number:1-16>Port_<n>_configuration of Ethernet Subsystem Intel FPGA IP Parameters: HSSI
    • Dynamic Reconfiguration
    • 100G Partial Reconfiguration
  • Added the following parameters to General Options in F-Tile Ethernet Subsystem Intel FPGA IP Parameters: Ethernet Subsystem –IP Configuration Tab table.
    • Enable debug endpoint for transceiver toolkit

    • Enable debug endpoint for Ethernet toolkit

    • Enable asynchronous adapter clocks
    • Enable dedicated CDR clock output
    • Include 40GE
    • Include 32bit sof CWBIN counters
  • Added AN channel location 0 under ANLT Options tab.
  • Added new chapter Subsystem IP Blocks.
    • Added new section AXI Stream Bridge.
    • Added IEEE 1588V2 PTP chapter.
  • Added Auto-Negotiation and Link Training chapter.
    • Added ANLT for E-Tile section.
    • Added ANLT for F-Tile section.
  • Added get_hssi_profile for E-Tile section.
  • Updated get_hssi_profile for F-Tile
  • Added set_hssi_profile for E-Tile section.
  • Updated set_hssi_profile for F-Tile.
  • Updated read_MAC_statistic table in Subsystem Abstraction Layer(SAL) Commands.
  • Updated get_mtu section.
  • Updated get_csr for E-Tile section.
  • Added Register Description for E-tile in Ncsi_get_link_status section.
  • Added a table signals mapping between 100G and 25G AXI-ST on the same interface in Dynamic Reconfiguration Extension Subsystem.
  • Updated F-Tile Address Maps section.
  • Updated E-Tile supported Example Design Variants table in Ethernet SS IP Design Example.
  • Added Steps to generate routing delay for F-Tile section in Running the Hardware Tests.
  • Added a new topic Clock Connections for SyncE Operation on F-Tile in Recommended Clock Connections.
  • Splitted F-Tile Register Map for Port Enabled with Ethernet Protocol into two tables in F-Tile Address Maps:
    • F-Tile Register Map for Port Enabled with Ethernet Protocol Port Enabled with Ethernet Protocol
    • F-Tile Register Map for per-channel Transceiver Reconfiguration Interface
  • Removed the DR support from the table F-Tile Support Example Design Variants in Ethernet SS IP Example Design.
2023.04.14 23.1
  • Updated instances of Transceiver Subsystem IP name to Ethernet Subsystem
  • Updated Introduction section with additional data rates and version.
  • Updated Ethernet Subsystem Intel FPGA IP Features table in Supported Features section.
  • Updated version to 23.1 in Getting Started section.
  • Updated Feature Description section with additional ports details.
  • Updated Supported Features section with additional ports details.
  • Updated Supported Ethernet Protocols table in Supported Features section.
  • Updated Ethernet Subsystem Intel FPGA IP Parameters: HSSI table in Parameter Editor Parameters section.
  • Updated E-Tile Ethernet Subsystem Intel FPGA IP Parameters: Ethernet Subsystem – IP Configuration Tab table in Parameter Editor Parameters section.
  • Updated F-Tile Ethernet Subsystem Intel FPGA IP Parameters: Ethernet Subsystem – IP Configuration Tab table in Parameter Editor Parameters section.
  • Added new section F-tile HSSI Port to PMA Channel Mapping.
  • Updated AXI-ST Tx Client Interface Signals and AXI-ST Rx Client Interface Signals tables in AXI-ST Client Interface.
  • Updated Serial Interface Signals table in Serial Interface section.
  • Updated Clock Signals table in Clocks section.
  • Updated Alternate Clock Connections for MAC Async Client FIFO section.
  • Updated F-tile Supported Example Design Variants table in HSSI SS IP Example Design section.
  • Added new section Supported Simulators.
  • Updated Running the Simulation Tests section.
2023.01.13 22.4
  • Updated Introduction section with additional data rates.
  • Updated Transceiver Subsystem Intel FPGA IP Features table in Supported Features section.
  • Updated version to 22.4 in Getting Started section.
  • Updated Supported Ethernet Protocols table in Supported Features section.
  • Updated Transceiver Subsystem Intel FPGA IP Parameters: HSSI table and F-Tile Transceiver Subsystem Intel FPGA IP Parameters: HSSI Subsystem – IP Configuration Tab table in Parameter Editor Parameters section.
  • Updated AXI-ST Tx Client Interface Signals table and AXI-ST Rx Client Interface Signals table in AXI-ST Client Interface section.
  • Updated Flow Control Signals table in Flow Control section.
  • Updated Serial Interface Signals table in Serial Interface section.
  • Updated Clocks Signals table in Clocks section.
  • Updated Value After Reset in Device Feature Header Hi section.
  • Updated Byte Offset information in the following sections:
    • Version
    • Feature List
    • Interface Attribute Port X Parameters
    • HSSI Command/Status
    • HSSI Read Data
    • HSSI Write Data
    • HSSI Ethernet Port X Status
  • Added F-tile ANLT Port Register Map and F-tile PTP Tile Adapter Register Map sections under Register Descriptions section.
2022.11.01 22.3 Initial release.