Ethernet Subsystem Intel® FPGA IP User Guide: Early Access Customer Release

Download PDF
ID 773413
Date 4/14/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Introduction 2. Feature Description 3. Ethernet Subsystem Parameters 4. Subsystem Abstraction Layer (SAL) 5. Dynamic Reconfiguration Extension Subsystem 6. Interfaces and Signals 7. Recommended Clock Connections 8. Register Descriptions 9. Ethernet SS IP Example Design 10. Document Revision History for Ethernet Subsystem Intel FPGA IP User Guide: Early Access Customer Release
1. Introduction x
1.1. Supported Features 1.2. Getting Started 1.3. Resource Utilization
2. Feature Description x
2.1. Ethernet Subsystem Intel FPGA IP Overview 2.2. Supported Features
3. Ethernet Subsystem Parameters x
3.1. Parameter Editor Parameters 3.2. E-Tile Port Enablement Guidelines and Restrictions 3.3. F-tile Ethernet Port to PMA Channel Mapping
4. Subsystem Abstraction Layer (SAL) x
4.1. Subsystem Abstraction Layer (SAL) Commands
4.1. Subsystem Abstraction Layer (SAL) Commands x
4.1.1. NOP(0x0) 4.1.2. get_hssi_profile 4.1.3. set_hssi_profile 4.1.4. read_MAC_statistic (0x3) 4.1.5. get_mtu(0x4) 4.1.6. set_csr for E-Tile (0x5) 4.1.7. set_csr for F-Tile 4.1.8. get_csr for E-Tile (0x6) 4.1.9. get_csr for F-Tile 4.1.10. enable_loopback for E-Tile (0x7) 4.1.11. enable_loopback for F-Tile 4.1.12. disable_loopback for E-Tile (0x8) 4.1.13. disable_loopback for F-Tile 4.1.14. Reset MAC Statistics (0x9) 4.1.15. set_mtu for F-Tile 4.1.16. Ncsi_get_link_status 4.1.17. Reserved 4.1.18. firmware_version (0xFF)
6. Interfaces and Signals x
6.1. AXI4 Interfaces 6.2. Serial Interface 6.3. Clocks 6.4. Resets
6.1. AXI4 Interfaces x
6.1.1. AXI-Lite CSR 6.1.2. AXI-ST Client Interface 6.1.3. AXI-ST PHY Direct 6.1.4. AXI-ST PTP 6.1.5. Flow Control
7. Recommended Clock Connections x
7.1. Driving Multiple Ports with the Same Clock 7.2. Alternate Clock Connections for MAC Async Client FIFO 7.3. F-Tile Clock Connections for PTP Synchronous and Asynchronous cases 7.4. Clock Connections for SyncE Operation 7.5. F-Tile PMA and FEC Direct PHY IP Clock Output
8. Register Descriptions x
8.1. Subsystem Registers 8.2. Port Registers 8.3. F-tile Address Maps 8.4. F-tile ANLT Port Register Map 8.5. F-tile PTP Tile Adapter Register Map
8.1. Subsystem Registers x
8.1.1. Device Feature Header Lo 8.1.2. Device Feature Header Hi 8.1.3. Feature GUID_L 8.1.4. Feature GUID_H 8.1.5. Feature CSR ADDR 8.1.6. Feature CSR Size Group 8.1.7. Version 8.1.8. Feature List 8.1.9. Interface Attribute Port X Parameters 8.1.10. HSSI Command/Status 8.1.11. HSSI Control/Address 8.1.12. HSSI Read Data 8.1.13. HSSI Write Data 8.1.14. HSSI Ethernet Port X Status
8.2. Port Registers x
8.2.1. E-Tile PTP Packet Classifier Registers
8.2.1. E-Tile PTP Packet Classifier Registers x
8.2.1.1. Recognized and Unrecognized Packet Counters 8.2.1.2. Parse Graph Specific Packet Counters
9. Ethernet SS IP Example Design x
9.1. Steps to Generate the Example Design 9.2. Supported Simulators 9.3. Running the Simulation Tests 9.4. Running the Hardware Tests
9.3. Running the Simulation Tests x
9.3.1. Steps to Simulate the Design Example
9.4. Running the Hardware Tests x
9.4.1. Supported Boards 9.4.2. Steps to Compile the Design Example for Hardware 9.4.3. Steps to Run the Design Example on Hardware
1. Introduction
2. Feature Description
3. Ethernet Subsystem Parameters
4. Subsystem Abstraction Layer (SAL)
5. Dynamic Reconfiguration Extension Subsystem
6. Interfaces and Signals
7. Recommended Clock Connections
8. Register Descriptions
9. Ethernet SS IP Example Design
10. Document Revision History for Ethernet Subsystem Intel FPGA IP User Guide: Early Access Customer Release

4.1.16. Ncsi_get_link_status

Ncsi_get_link_status SAL command is intended to provide software abstraction for obtaining all the necessary status in single command to comply with get link status CSR requirement in NCSI specification. Users use this command to obtain the ethernet link status per the following table.
HSSI Read Data Fields ANLT enable ANLT disable
[31:22] Reserved 0 N/A (Return 0) N/A (Return 0)
[21:21] OEM Link Speed Valid 0b = OEM link settings are invalid.

1b = OEM link settings are valid

 N/A (Return 0) N/A (Return 0)
[20:20] SerDes Link

SerDes status (see 4.18")

0b = SerDes not used

1b = SerDes used

This field is mandatory

0x118 tx_lanes_stable AND

0x1084 rx_aligned

0x118 tx_lanes_stable AND

0x1084 rx_aligned
[19:18] Link Partner Advertised Flow Control

00b = Link partner is not pause capable.

01b = Link partner supports symmetric pause.

10b = Link partner supports asymmetric pause toward link partner.

11b = Link partner supports both symmetric and asymmetric pause.

Valid when: SerDes Flag = 0b

Auto-Negotiate = 1b

Auto-Negotiate Complete = 1b

This field is mandatory

0x31C Link partner PAUSE bits[12:10] (bit 12 - not defined)

00b = 0x31C (bit 10 and bit 11 = 0)

01b = 0x31C (bit 10 = 1)

10b = 0x31C (bit 11 = 1)

11b = 0x31C (bit 10 or bit 11 = 1)

0
[17:17] Rx Flow Control Flag

0b = Reception of Pause frames by the NC from the external network interface is disabled.

1b = Reception of Pause frames by the NC from the external network interface is enabled.

This field is mandatory.

Rx Flow Control Flag

1'b1 = 0x1260 en_rx_pause (non zero)

1'b0 = 0x1260 en_rx_pause (all zero)

Rx Flow Control Flag

1'b1 = 0x1260 en_rx_pause (non zero)

1'b0 = 0x1260 en_rx_pause (all zero)
[16:16] Tx Flow Control Flag

0b = Transmission of Pause frames by the NC onto the external network interface is disabled.

1b = Transmission of Pause frames by the NC onto the external network interface is enabled.

This field is mandatory interface.

This field is mandatory.

Tx Flow Control Flags

1'b1 = 0x122c en_pfc_port (non zero)

1'b0 = 0x122c en_pfc_port (all zero)

Tx Flow Control Flags

1'b1 = 0x122c en_pfc_port (non zero)

1'b0 = 0x122c en_pfc_port (all zero)

[15:15] Link Partner Advertised Speed and Duplex 10THD

1b = Link Partner is 10BASE-T half-duplex capable.

Valid when:

SerDes Flag = 0b

Auto-Negotiate Flag = 1b

Auto-Negotiate Complete = 1b

This field is mandatory.

 0 0
[14:14] Link Partner Advertised Speed and Duplex 10TFD

1b = Link Partner is 10BASE-T full-duplex capable.

Valid when:

SerDes Flag = 0b

Auto-Negotiate Flag = 1b

Auto-Negotiate Complete = 1b

This field is mandatory.

 0 0
[13:13] Link Partner Advertised Speed and Duplex 100TXHD

1b = Link Partner is 100BASE-TX half-duplex capable.

Valid when:

SerDes Flag = 0b

Auto-Negotiate Flag = 1b

Auto-Negotiate Complete = 1b

This field is mandatory.

 0 0
[12:12] Link Partner Advertised Speed and Duplex 100TXFD

1b = Link Partner is 100BASE-TX full-duplex capable.

Valid when:

SerDes Flag = 0b

Auto-Negotiate Flag = 1b

Auto-Negotiate Complete = 1b

This field is mandatory

 0 0
[11:11] Link Partner Advertised Speed and Duplex 100T4

1b = Link Partner is 100BASE-T4 capable.

Valid when:

SerDes Flag = 0b

Auto-Negotiate Flag = 1b

Auto-Negotiate Complete = 1b

This field is mandatory

 0 0
[10:10] Link Partner Advertised Speed and Duplex 1000THD

1b = Link Partner is 1000BASE-T half-duplex capable.

Valid when:

SerDes Flag = 0b

Auto-Negotiate Flag = 1b

Auto-Negotiate Complete = 1b

This field is mandatory.

 0 0
[9:9] Link Partner Advertised Speed and Duplex 1000TFD

1b = Link Partner is 1000BASE-T full-duplex capable.

Valid when:

SerDes Flag = 0b

Auto-Negotiate Flag = 1b

Auto-Negotiate Complete = 1b

This field is mandatory.

 0 0
[8:8] Reserved None 0 0
[7:7] Parallel Detection Flag

1b = Link partner did not support auto-negotiation and parallel detection was used to get link.

This field contains 0b if Parallel Detection was not used to obtain link.

 0x308 [7:7] an_lp_apability 0
[6:6] Auto Negotiate Complete

1b = Auto-negotiation has completed.

This includes if auto-negotiation was completed using Parallel

Detection. Always returns 0b if auto-negotiation is not supported or is not enabled.

This field is mandatory if the Auto Negotiate Flag is supported.

 0x308 [2:2] an_complete 0
[5:5] Auto Negotiate Flag

1b = Auto-negotiation is enabled.

This field always returns 0b if auto-negotiation is not supported.

This field is mandatory if supported by the controller.

 0x300 [0:0] enable_an 0
[4:1] Speed and duplex

0x0 = Auto-negotiate not complete [per IEEE 802.3], SerDes

Flag = 1b, or no Highest Common Denominator (HCD) from the following options (0x1 through 0x8) was found.

0x1 = 10BASE-T half-duplex

0x2 = 10BASE-T full-duplex

0x3 = 100BASE-TX half-duplex

0x4 = 100BASE-T4

0x5 = 100BASE-TX full-duplex

0x6 = 1000BASE-T half-duplex

0x7 = 1000BASE-T full-duplex

0x8 = 10G-BASE-T support

0x9 = 20 Gbps (optional for NC-SI 1.1, RESERVED for NCSI 1.0)

0xA = 25 Gbps (optional for NC-SI 1.1, RESERVED for NCSI 1.0)

0xB = 40 Gbps (optional for NC-SI 1.1, RESERVED for NCSI 1.0)

0xC = 50 Gbps (optional for NC-SI 1.1, RESERVED for NCSI 1.0)

0xD = 100 Gbps (optional for NC-SI 1.1, RESERVED for NCSI 1.0)

0xE = 2.5 Gbps (optional for NC-SI 1.1, RESERVED for NCSI 1.0)

0xF = Use values defined in Enhanced Speed and Duplex field starting at bit 24 (optional for NC-SI 1.1, RESERVED for NC-SI 1.0)

Except when SerDes = 1b, the value may reflect forced link setting.

0x0 = 0x308 (Bit [11:11] negotiation_faiilure = 1) negotiation_faiilure

0xA = C2 (Bit 17 = 1 or Bit 18 = 1)

0xB = C2 (Bit 13 = 1 or Bit 14 = 1)

0xC = C2 (Bit 19 = 1)

0xD = C2 (Bit 15 or Bit 16 or Bit 20 or Bit 22 = 1)

Remaining all zero

 0
[0:0] Link Flag

0b = Link is down

1b = Link is up

This field is mandatory.

 0x308 [6:6] an_status

0x118 tx_lanes_stable AND 0x1084 rx_aligned
Level Two Title