Ethernet Subsystem Intel® FPGA IP User Guide: Early Access Customer Release

ID 773413
Date 4/14/2023
Public

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Document Table of Contents

6.3. Clocks

Table 29.  Clock Signals
Signal Name Direction Description
i_p<n>_clk_ref[2:0] In

The input clock i_clk_ref is the reference clock for the high-speed serial clocks and the datapath parallel clocks.

E-tile: 3 reference clocks will be used with i_clk_ref[2:0] as defined below:

i_clk_ref[0] - 156.25 MHz

i_clk_ref[1] - 184.32 MHz

i_clk_ref[2] - 153.6 MHz

F-tile: 2 reference clocks will be used with i_clk_ref[1:0] defined as follows:

i_clk_ref[0]- FGT refclk clock

i_clk_ref[1] - FHT refclk clock

The System PLL and Common PLL reference clock configuration is selected through F-Tile Reference and System PLL Clock Intel FPGA IP drives this clock.

  • 156.25 MHz is the recommended frequency. Supported when using FHT PMA or when auto-negotiation and link training is enabled.
  • 312.5 MHz when using FGT PMA without auto-negotiation and link training
  • 322.265625 MHz when using FGT PMA without auto-negotiation and link training

By default, FGT Refclk #2 will be used in i_clk_ref[0] and FHT Refclk #0 will be used in i_clk_ref[1] will be used as reference clock for System PLL/Common PLL with frequency configured to 156.25 MHz. You can specify other frequency or reference clock for System PLL/Common PLL in the F-Tile Ethernet Intel FPGA Hard IP PMA reference frequency IP parameter and in the F-Tile Reference and System PLL Clock Intel FPGA IP FGT refclk frequency/FHT refclk frequency IP parameter.

i_p<n>_clk_tx In

TX data path clock.

This clock drives the active TX interface for the port.

This clock must be sourced from o_p<n>_clk_pll unless Enable asynchronous adapter clocks is selected.

i_p<n>_clk_rx In

RX data path clock.

This clock drives the active TX interface for the port.

This clock must be sourced from o_p<n>_clk_pll unless Enable asynchronous adapter clocks selected.

i_p<n>_clk_tx_tod In

Clock associated with TX Time-of-Day (ToD) input.

Basic Accuracy Mode: Connect to any clock with frequency below:

  • 10G: 390.625 MHz (F-tile)
  • 25G-400G: 390.625 MHz (F-tile)
  • 10G-100G: 402.83 MHz (E-tile)

Advanced Accuracy Mode:

The o_p<n>_clk_tx_div must drive this clock. The clock frequency varies based on the Ethernet variant:

  • 10G:156.25 MHz
  • 25G-400G:390.625 MHz

For more information, refer to the PTP Timestamp Accuracy section in E-tile Hard IP User Guide section and PTP Timestamp Accuracy section in F-tile Hard IP User Guide.

i_p<n>_clk_rx_tod In

Clock associated with RX Time-of-Day (ToD) input.

Basic Accuracy Mode: Connect to any clock with frequency below.

  • 10G-400G: 390.625 MHz

Advanced Accuracy Mode:

The o_p<n>_clk_rec_div must drive this clock. The clock frequency varies based on the Ethernet variant:

  • 10GbE:156.25 MHz
  • 25GbE-400GbE:390.625 MHz

For more information, refer to the E-tile Hard IP User Guide, PTP Timestamp Accuracy section and F-tile Hard IP User Guide, PTP Timestamp Accuracy section.

i_p<n>_clk_ptp_sample In

Sample clock for PTP measurement.

This is an external clock provided to the design with frequency of 114.285714 MHz (with required period of 8.75 ns) with ± 100 ppm.

Note: Applicable only when you set the PTP Accuracy Mode parameter to Advanced Mode.

For more information, refer to the E-tile Hard IP User Guide, PTP Timestamp Accuracy section and F-tile Hard IP User Guide, PTP Timestamp Accuracy section.

o_p<n>_clk_pll Out

Hard IP for Ethernet block clock.

E-tile: Supports the following clock frequencies:

  • 402.83203125 MHz for 25G and 100G with optional RS-FEC(528,514) channels.
  • 402.83203125 MHz for 10G PTP and 25G PTP channels.
  • 415.0390625 MHz for 100G with RS- FEC(544,514) channel.
  • 161.1328125 MHz for 10G channels.

This clock is reliable only after o_tx_pll_locked is asserted.

F-tile:

System PLL clock

Clock derived from the F-Tile System PLL associated with the Ethernet IP port. The o_p<n>clk_pll frequency is equal to PLL frequency divided by 2. The following shows the o_p<n>clk_pll frequency unless you enabled custom system PLL frequency.

Supports the following frequencies:

  • 402.83203125 MHz or higher for all Ethernet modes without FEC, with IEEE 802.3 BASE-R Firecode (CL74), or IEEE 802.3 RS(528,514) (CL91). The system PLL must be of 805.6640625 MHz frequency or higher.
  • 415.0390625 MHz or higher for all Ethernet modes with IEEE 802.3 RS(544,514) (CL134), with Ethernet Technology Consortium RS(272, 258). The system PLL must be of 830.078125 MHz frequency or higher.
  • 161.1328125 MHz or higher for 10GE without enabled PTP. The system PLL must be of 322.265625 MHz frequency or higher.
  • Custom system PLL frequency divided by 2, if custom system PLL frequency is used
o_p<n>_clk_tx_div Out

Hard IP for Ethernet block clock times 64/66.

E-tile: Supports the following clock frequencies:

  • 390.625 MHz for 25G and 100G with optional RS-FEC (528,514) PORT.
  • 402.4621 MHz for 100G with RS-FEC (544,514).
  • 156.25 MHz for 10G PORT.
  • 805.66 MHz for 25G PTP channel.
  • 322.265625 MHz for 10G PTP channel.

This clock is reliable only after o_tx_pll_locked is asserted.

F-tile: Supports the following frequencies:

  • 156.25 MHz for 10GE
  • 312.5 MHz for 40GE
  • 390.625 MHz for all other Ethernet modes

Clock recovered from the TX SERDES rate divided by either 33/66/68, depending on the FEC mode and Ethernet mode parameters. The o_clk_tx_div is equal to:

  • TX SERDES rate divided by 33 for 40GE.
  • TX SERDES rate divided by 66 when FEC mode parameter is set to one of the following:
    • None except for 40GE
    • IEEE 802.3 BASE-R Firecode (CL74)
    • IEEE 802.3 RS(528,514) (CL91)
  • TX SERDES rate divided by 68 when FEC mode parameter is set to one of the following:
    • IEEE 802.3 RS(544,514) (CL134)
    • Ethernet Technology Consortium RS(272, 258)
o_p<n>_clk_rec_div64 Out Derived from RX recovered clock. This clock supports the SyncE standard.

E-tile:

The RX recovered clock frequency is:

  • 161.1328125 MHz ±100 ppm for 10G PORT.
  • 402.83203125 MHz ±100 ppm for 25G PORT.
  • 402.83203125 MHz ±100 ppm for 100G with optionalRS-FEC (528,514) PORT.
  • 415.0390625 MHz ±100 ppm for 100G with RS- FEC (544,514) PORT.

This clock is reliable only after o_cdr_lock[n] is asserted.

When using this clock for Synchronous Ethernet, the expected usage is that you drive the TX transceiver reference clock with a filtered and divided version of o_p<n>_clk_rec_div64 or o_p<n>_clk_rec_div, to ensure the receive and transmit functions remain synchronized. To do so you must include an additional component on your board.The IP core does not provide filtering.

Note: The RX recovered clock is not available for PTP PORT when PTP enabled.

F-tile:

Supports the following frequencies:

  • 161.1328125 MHz ± 200 PPM for 10GE/40GE
  • 402.83203125 MHz ± 200 PPM for Ethernet modes without FEC (except 10GE and 40GE), with IEEE 802.3 BASE-R Firecode (CL74), and IEEE 802.3 RS(528,514) (CL91)
  • 415.0390625 MHz ± 200 PPM for Ethernet modes with IEEE 802.3 RS(544,514) (CL134) and Ethernet Technology Consortium RS(272, 258)

Clock derived from RX recovered clock, divided by 64.

o_p<n>_clk_rec_div Out

Derived from RX recovered clock. This clock supports the Synchronous Ethernet standard.

E-tile:

The RX recovered clock frequency is:

  • 156.25 MHz ±100 ppm for 10GE port.
  • 390.625 MHz ±100 ppm for 25GE port.
  • 390.625 MHz ±100 ppm for 100GE with optional RS-FEC (528,514) port.
  • 402.4621 MHz ±100 ppm for 100G with optional RS-FEC (528,514) port.

This clock is reliable only after o_cdr_lock[n] is asserted.

When using this clock for Synchronous Ethernet, the expected usage is that you drive the TX transceiver PLL reference clock with a filtered and divided version of o_clk_rec_div64 or o_clk_rec_div, to ensure the receive and transmit functions remain synchronized. To do so you must include an additional component on your board.

The IP core does not provide filtering.

Note: The RX recovered clock is not available for PTP PORT when PTP enabled.

F-tile:

Supports the following frequencies:

  • 156.25 MHz ± 200PPM for 10GE
  • 312.50 MHz ± 200PPM for 40GE
  • 390.625 MHz ± 200PPM for all other Ethernet modes

Clock derived from the RX recovered clock divided by either 33/66/68, depending on the FEC mode parameter. The o_clk_rec_div is equal to:

  • RX SERDES rate divided by 33 for 40GE
  • RX SERDES rate divided by 66 when FEC mode parameter is set to one of the following:
    • None except for 40GE
    • IEEE 802.3 BASE-R Firecode (CL74)
    • IEEE 802.3 RS(528,514) (CL91)
  • RX SERDES rate divided by 68 when FEC mode parameter is set to one of the following:
    • IEEE 802.3 RS(544,514) (CL134)
    • Ethernet Technology Consortium RS(272, 258)
o_ehip<n/2>_ptp_clk_pll Out

For E-tile, PLL clock outputs from PTP channels.

There are 2 PTP channels for each enabled EHIP Core. These clocks are available only if PTP is enabled in any one of the channels within the EHIP core.

Supports the following clock frequencies:

  • 402.83203125 MHz for 25G and 100G with optionalRS-FEC(528,514) port.
  • 415.0390625 MHz for 100G with RS- FEC(544,514) channel.
  • 161.1328125 MHz for 10G port.
This clock is reliable only after o_tx_pll_locked is asserted.
o_ehip<n/2>_ptp_clk_tx_div Out

For E-tile, PLL clock outputs from PTP channels.

There are 2 PTP channels for each enabled EHIP Core. These clocks are available only if PTP is enabled in any one of the channels within the EHIP core.

Hard IP for Ethernet block clock times 64/66. Supports the following clock frequencies:

  • 390.625 MHz for 25G and 100G with optional RS-FEC (528,514) port.
  • 402.4621 MHz for 100G with RS-FEC (544,514).
  • 156.25 MHz for 10G port.
  • 805.66 MHz for 25G PTP channel.
  • 322.265625 MHz for 10G PTP channel.

This clock is reliable only after o_tx_pll_locked is asserted.

o_ehip<n/2>_ptp_clk_rec_div64 Out

For E-tile, these are PLL clock outputs from PTP channels.

There are 2 PTP channels for each enabled EHIP Core. These clocks are available only if PTP is enabled in any one of the channels with in the EHIP core.

Derived from RX recovered clock. This clock supports the SyncE standard.

The RX recovered clock frequency is:

  • 161.1328125 MHz ±100 ppm for 10G port.
  • 402.83203125 MHz ±100 ppm for 25G port.
  • 402.83203125 MHz ±100 ppm for 100G with optional RS-FEC (528,514) port.
  • 415.0390625 MHz ±100 ppm for 100G with RS- FEC (544,514) port.
This clock is reliable only after o_cdr_lock[n] is asserted.

When using this clock for Synchronous Ethernet, the expected usage is that you drive the TX transceiver reference clock with a filtered and divided version of o_clk_rec_div64 or o_clk_rec_div66, to ensure the receive and transmit functions remain synchronized. To do so you must include an additional component on your board. The IP core does not provide filtering.

Note: The RX recovered clock is not available for PTP PORT when PTP enabled.
o _ehip<n/2>_clk_rec_div Out

For E-tile, these are PLL clock outputs from PTP channels.

There are 2 PTP channels for each enabled EHIP Core. These clocks are available only if PTP is enabled in any one of the channels with in the EHIP core.

Derived from RX recovered clock. This clock supports the SynchE standard.

The RX recovered clock frequency is:

  • 156.25 MHz ±100 ppm for 10G port.
  • 390.625 MHz ±100 ppm for 25G port.
  • 390.625 MHz ±100 ppm for 100G with optional RS-FEC(528,514) port.
  • 402.4621 MHz ±100 ppm for 100G with optional RS-FEC (528,514) port.

This clock is reliable only after o_cdr_lock[n] is asserted.

When using this clock for Synchronous Ethernet, the expected usage is that you drive the TX transceiver PLL reference clock with a filtered and divided version of o_clk_rec_div64 or o_clk_rec_div66, to ensure the receive and transmit functions remain synchronized. To do so you must include an additional component on your board. The IP core does not provide filtering.

Note: The RX recovered clock is not available for PTP PORT when PTP enabled.
i_p<n>_async_clk_tx In

For E-tile, this clock drives the TX interface for 25GbE profile when Asynchronous mode is enabled.

The clock frequency must be within 390.625 MHz and 402.83203125 MHz.

i_p<n>_async_clk_rx In

For E-tile, this clock drives the RX interface for 25GbE profile when Asynchronous mode is enabled.

The clock frequency must be within 390.625 MHz and 402.83203125 MHz.