Ethernet Subsystem Intel® FPGA IP User Guide: Early Access Customer Release

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ID 773413
Date 4/14/2023
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Feature Description 3. Ethernet Subsystem Parameters 4. Subsystem Abstraction Layer (SAL) 5. Dynamic Reconfiguration Extension Subsystem 6. Interfaces and Signals 7. Recommended Clock Connections 8. Register Descriptions 9. Ethernet SS IP Example Design 10. Document Revision History for Ethernet Subsystem Intel FPGA IP User Guide: Early Access Customer Release
1. Introduction x
1.1. Supported Features 1.2. Getting Started 1.3. Resource Utilization
2. Feature Description x
2.1. Ethernet Subsystem Intel FPGA IP Overview 2.2. Supported Features
3. Ethernet Subsystem Parameters x
3.1. Parameter Editor Parameters 3.2. E-Tile Port Enablement Guidelines and Restrictions 3.3. F-tile Ethernet Port to PMA Channel Mapping
4. Subsystem Abstraction Layer (SAL) x
4.1. Subsystem Abstraction Layer (SAL) Commands
4.1. Subsystem Abstraction Layer (SAL) Commands x
4.1.1. NOP(0x0) 4.1.2. get_hssi_profile 4.1.3. set_hssi_profile 4.1.4. read_MAC_statistic (0x3) 4.1.5. get_mtu(0x4) 4.1.6. set_csr for E-Tile (0x5) 4.1.7. set_csr for F-Tile 4.1.8. get_csr for E-Tile (0x6) 4.1.9. get_csr for F-Tile 4.1.10. enable_loopback for E-Tile (0x7) 4.1.11. enable_loopback for F-Tile 4.1.12. disable_loopback for E-Tile (0x8) 4.1.13. disable_loopback for F-Tile 4.1.14. Reset MAC Statistics (0x9) 4.1.15. set_mtu for F-Tile 4.1.16. Ncsi_get_link_status 4.1.17. Reserved 4.1.18. firmware_version (0xFF)
6. Interfaces and Signals x
6.1. AXI4 Interfaces 6.2. Serial Interface 6.3. Clocks 6.4. Resets
6.1. AXI4 Interfaces x
6.1.1. AXI-Lite CSR 6.1.2. AXI-ST Client Interface 6.1.3. AXI-ST PHY Direct 6.1.4. AXI-ST PTP 6.1.5. Flow Control
7. Recommended Clock Connections x
7.1. Driving Multiple Ports with the Same Clock 7.2. Alternate Clock Connections for MAC Async Client FIFO 7.3. F-Tile Clock Connections for PTP Synchronous and Asynchronous cases 7.4. Clock Connections for SyncE Operation 7.5. F-Tile PMA and FEC Direct PHY IP Clock Output
8. Register Descriptions x
8.1. Subsystem Registers 8.2. Port Registers 8.3. F-tile Address Maps 8.4. F-tile ANLT Port Register Map 8.5. F-tile PTP Tile Adapter Register Map
8.1. Subsystem Registers x
8.1.1. Device Feature Header Lo 8.1.2. Device Feature Header Hi 8.1.3. Feature GUID_L 8.1.4. Feature GUID_H 8.1.5. Feature CSR ADDR 8.1.6. Feature CSR Size Group 8.1.7. Version 8.1.8. Feature List 8.1.9. Interface Attribute Port X Parameters 8.1.10. HSSI Command/Status 8.1.11. HSSI Control/Address 8.1.12. HSSI Read Data 8.1.13. HSSI Write Data 8.1.14. HSSI Ethernet Port X Status
8.2. Port Registers x
8.2.1. E-Tile PTP Packet Classifier Registers
8.2.1. E-Tile PTP Packet Classifier Registers x
8.2.1.1. Recognized and Unrecognized Packet Counters 8.2.1.2. Parse Graph Specific Packet Counters
9. Ethernet SS IP Example Design x
9.1. Steps to Generate the Example Design 9.2. Supported Simulators 9.3. Running the Simulation Tests 9.4. Running the Hardware Tests
9.3. Running the Simulation Tests x
9.3.1. Steps to Simulate the Design Example
9.4. Running the Hardware Tests x
9.4.1. Supported Boards 9.4.2. Steps to Compile the Design Example for Hardware 9.4.3. Steps to Run the Design Example on Hardware
1. Introduction
2. Feature Description
3. Ethernet Subsystem Parameters
4. Subsystem Abstraction Layer (SAL)
5. Dynamic Reconfiguration Extension Subsystem
6. Interfaces and Signals
7. Recommended Clock Connections
8. Register Descriptions
9. Ethernet SS IP Example Design
10. Document Revision History for Ethernet Subsystem Intel FPGA IP User Guide: Early Access Customer Release

3.2. E-Tile Port Enablement Guidelines and Restrictions

Ethernet Subsystem Intel FPGA IP for Agilex devices provides up to 16 Ethernet ports. As the IP is implemented based on Intel Agilex E-tile Hard IP for Ethernet Intel FPGA IP Core, the ports are mapped to E-tile transceiver channels and channel placement rules of the Hard IP are also applicable to Subsystem IP. PTP channels are not configurable from the IP GUI.
Table 9.  Subsystem Port – Transceiver Channel Mapping
Subsystem Port E-tileTransceiver Channel EHIP Core
0 0 0
1 1 0
2 2 0
3 3 0
- PTP Channel (4) 0
- PTP Channel (5) 0
- PTP Channel (6) 1
- PTP Channel (7) 1
4 8 1
5 9 1
6 10 1
7 11 1
8 12 2
9 13 2
10 14 2
11 15 2
- PTP Channel (16) 2
- PTP Channel (17) 2
- PTP Channel (18) 3
- PTP Channel (19) 3
12 20 3
13 21 3
14 22 3
15 23 3

General guidelines of Subsystem port configurations:

  • Enable the same number of port(s) as specified in NUM_ENABLED_PORTS parameter.
  • Click File > Refresh System whenever you modify port configurations to ensure parameter options are displayed correctly.
  • 100G CAUI-4 is considered as a single port configuration and can only be enabled on port 0/4/8/12. When any of the four ports are configured as 100G CAUI-4 profile, the remaining three ports in the same EHIP Core will be hidden in the IP GUI.
  • When configuration of a port matches the configuration of the previous port in the same EHIP Core, this message will be displayed at the bottom of the port configuration: 
hssi_ss:PORT <n> configuration matches with PORT <n-1> configuration
Figure 2. Matching Ports Configurations

In the IP configuration tab, the parameters are only available to be configured for the first port. Parameters of subsequent matching port(s) are hidden and would match the settings of the first port.

  • Like E-tile Hard IP for Ethernet channel placement, the E-tile transceiver requires RS-FEC to be enabled on contiguous ports only.
  • For EHIP Core 1 (Port 4/5/6/7) and EHIP Core 3 (Port 12/13/14/15), PTP-enabled multi-port design must be configured in sequence, starting from the first port of the EHIP Core. For example, enable PTP starting from Port 4, followed by Port 5, 6 and 7 for 4-port PTP design on EHIP Core 1.
  • For EHIP Core 0 (Port 0/1/2/3) and EHIP Core 2 (Port 8/9/10/11), PTP- enabled multi-port design must be configured in reverse sequence, starting from the last port of the EHIP Core. For example, enable PTP starting from Port 3, followed by Port 2, 1 and 0 for 4-port PTP design on EHIP Core 0.

If the expected sequence is not observed for EHIP Core 0 and 2, the IP Core will automatically enable subsequent PTP port(s) to align with E-tile channel placement rules. For example, if Port 0 is enabled with PTP before Ports 3,2,1 is configured, the IP Core will automatically enable Ports 3,2,1 with PTP.

Figure 3. IP Core will Automatically Enable Subsequent PTP Port(s)
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