Ethernet Subsystem Intel® FPGA IP User Guide: Early Access Customer Release

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ID 773413
Date 4/14/2023
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Feature Description 3. Ethernet Subsystem Parameters 4. Subsystem Abstraction Layer (SAL) 5. Dynamic Reconfiguration Extension Subsystem 6. Interfaces and Signals 7. Recommended Clock Connections 8. Register Descriptions 9. Ethernet SS IP Example Design 10. Document Revision History for Ethernet Subsystem Intel FPGA IP User Guide: Early Access Customer Release
1. Introduction x
1.1. Supported Features 1.2. Getting Started 1.3. Resource Utilization
2. Feature Description x
2.1. Ethernet Subsystem Intel FPGA IP Overview 2.2. Supported Features
3. Ethernet Subsystem Parameters x
3.1. Parameter Editor Parameters 3.2. E-Tile Port Enablement Guidelines and Restrictions 3.3. F-tile Ethernet Port to PMA Channel Mapping
4. Subsystem Abstraction Layer (SAL) x
4.1. Subsystem Abstraction Layer (SAL) Commands
4.1. Subsystem Abstraction Layer (SAL) Commands x
4.1.1. NOP(0x0) 4.1.2. get_hssi_profile 4.1.3. set_hssi_profile 4.1.4. read_MAC_statistic (0x3) 4.1.5. get_mtu(0x4) 4.1.6. set_csr for E-Tile (0x5) 4.1.7. set_csr for F-Tile 4.1.8. get_csr for E-Tile (0x6) 4.1.9. get_csr for F-Tile 4.1.10. enable_loopback for E-Tile (0x7) 4.1.11. enable_loopback for F-Tile 4.1.12. disable_loopback for E-Tile (0x8) 4.1.13. disable_loopback for F-Tile 4.1.14. Reset MAC Statistics (0x9) 4.1.15. set_mtu for F-Tile 4.1.16. Ncsi_get_link_status 4.1.17. Reserved 4.1.18. firmware_version (0xFF)
6. Interfaces and Signals x
6.1. AXI4 Interfaces 6.2. Serial Interface 6.3. Clocks 6.4. Resets
6.1. AXI4 Interfaces x
6.1.1. AXI-Lite CSR 6.1.2. AXI-ST Client Interface 6.1.3. AXI-ST PHY Direct 6.1.4. AXI-ST PTP 6.1.5. Flow Control
7. Recommended Clock Connections x
7.1. Driving Multiple Ports with the Same Clock 7.2. Alternate Clock Connections for MAC Async Client FIFO 7.3. F-Tile Clock Connections for PTP Synchronous and Asynchronous cases 7.4. Clock Connections for SyncE Operation 7.5. F-Tile PMA and FEC Direct PHY IP Clock Output
8. Register Descriptions x
8.1. Subsystem Registers 8.2. Port Registers 8.3. F-tile Address Maps 8.4. F-tile ANLT Port Register Map 8.5. F-tile PTP Tile Adapter Register Map
8.1. Subsystem Registers x
8.1.1. Device Feature Header Lo 8.1.2. Device Feature Header Hi 8.1.3. Feature GUID_L 8.1.4. Feature GUID_H 8.1.5. Feature CSR ADDR 8.1.6. Feature CSR Size Group 8.1.7. Version 8.1.8. Feature List 8.1.9. Interface Attribute Port X Parameters 8.1.10. HSSI Command/Status 8.1.11. HSSI Control/Address 8.1.12. HSSI Read Data 8.1.13. HSSI Write Data 8.1.14. HSSI Ethernet Port X Status
8.2. Port Registers x
8.2.1. E-Tile PTP Packet Classifier Registers
8.2.1. E-Tile PTP Packet Classifier Registers x
8.2.1.1. Recognized and Unrecognized Packet Counters 8.2.1.2. Parse Graph Specific Packet Counters
9. Ethernet SS IP Example Design x
9.1. Steps to Generate the Example Design 9.2. Supported Simulators 9.3. Running the Simulation Tests 9.4. Running the Hardware Tests
9.3. Running the Simulation Tests x
9.3.1. Steps to Simulate the Design Example
9.4. Running the Hardware Tests x
9.4.1. Supported Boards 9.4.2. Steps to Compile the Design Example for Hardware 9.4.3. Steps to Run the Design Example on Hardware
1. Introduction
2. Feature Description
3. Ethernet Subsystem Parameters
4. Subsystem Abstraction Layer (SAL)
5. Dynamic Reconfiguration Extension Subsystem
6. Interfaces and Signals
7. Recommended Clock Connections
8. Register Descriptions
9. Ethernet SS IP Example Design
10. Document Revision History for Ethernet Subsystem Intel FPGA IP User Guide: Early Access Customer Release

6.1.3. AXI-ST PHY Direct

The AXI-ST PHY Direct Interface is available when user select below profiles as Subsystem Profiles for specific port.

Ethernet PMA/FEC/PCS-Direct, MII, General PMA/FEC/PCS-Direct, OTN, Flex-E, TSE PCS

Please refer to AXI-ST Client Interface section for detail on the existence of AXI-ST PHY Direct and AXI-ST Client interface when DR Extension Subsystem is enabled.

Table 19.  Tx PHY Direct Functional Signals
Signal Name Direction Type Description
p{0..NUM_PORT}_app_ss_st_txphydirect_clk In Clock The TX clock for the IP core that drives the channel.
p{0..NUM_PORT}_app_ss_st_ txphydirect_areset_n[PORTX_CHANNEL-1:0] In Reset Asynchronous reset.
p{0..NUM_PORT}_app_ss_st_ txphydirect_tdata[PORTX_CHANNEL-1:0][ PORTX_DATA_WIDTH-1:0] In Data Tx PHY Direct parallel data
p{0..NUM_PORT}_ss_app_st_ txphydirect_tready [PORTX_CHANNEL-1:0] Out Status Ready signal for PHY Direct data
p{0..NUM_PORT}_app_ss_st_ txphydirect_tvalid [PORTX_CHANNEL-1:0] In Status Valid signal for PHY Direct data
Table 20.  Rx PHY Direct Functional Signals
Signal Name Direction Type Description
p{0..NUM_PORT}_app_ss_st_rxphydirect _clk In Clock

The RX clock for the IP core that drives the channel.
p{0..NUM_PORT}_app_ss_st_ rxphydirect_areset_n[PORTX_CHANNEL-1:0] In Reset Asynchronous reset.
p{0..NUM_PORT}_ss_app_st_ rxphydirect_tdata[PORTX_CHANNEL-1:0][PORTX_DATA_WIDTH-1:0] Out Data Rx PHY Direct parallel data.
p{0..NUM_PORT}_ss_app_st_ rxphydirect_tvalid Out Status Valid signal for PHY Direct data.
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