Ethernet Subsystem Intel® FPGA IP User Guide: Early Access Customer Release

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ID 773413
Date 4/14/2023
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Feature Description 3. Ethernet Subsystem Parameters 4. Subsystem Abstraction Layer (SAL) 5. Dynamic Reconfiguration Extension Subsystem 6. Interfaces and Signals 7. Recommended Clock Connections 8. Register Descriptions 9. Ethernet SS IP Example Design 10. Document Revision History for Ethernet Subsystem Intel FPGA IP User Guide: Early Access Customer Release
1. Introduction x
1.1. Supported Features 1.2. Getting Started 1.3. Resource Utilization
2. Feature Description x
2.1. Ethernet Subsystem Intel FPGA IP Overview 2.2. Supported Features
3. Ethernet Subsystem Parameters x
3.1. Parameter Editor Parameters 3.2. E-Tile Port Enablement Guidelines and Restrictions 3.3. F-tile Ethernet Port to PMA Channel Mapping
4. Subsystem Abstraction Layer (SAL) x
4.1. Subsystem Abstraction Layer (SAL) Commands
4.1. Subsystem Abstraction Layer (SAL) Commands x
4.1.1. NOP(0x0) 4.1.2. get_hssi_profile 4.1.3. set_hssi_profile 4.1.4. read_MAC_statistic (0x3) 4.1.5. get_mtu(0x4) 4.1.6. set_csr for E-Tile (0x5) 4.1.7. set_csr for F-Tile 4.1.8. get_csr for E-Tile (0x6) 4.1.9. get_csr for F-Tile 4.1.10. enable_loopback for E-Tile (0x7) 4.1.11. enable_loopback for F-Tile 4.1.12. disable_loopback for E-Tile (0x8) 4.1.13. disable_loopback for F-Tile 4.1.14. Reset MAC Statistics (0x9) 4.1.15. set_mtu for F-Tile 4.1.16. Ncsi_get_link_status 4.1.17. Reserved 4.1.18. firmware_version (0xFF)
6. Interfaces and Signals x
6.1. AXI4 Interfaces 6.2. Serial Interface 6.3. Clocks 6.4. Resets
6.1. AXI4 Interfaces x
6.1.1. AXI-Lite CSR 6.1.2. AXI-ST Client Interface 6.1.3. AXI-ST PHY Direct 6.1.4. AXI-ST PTP 6.1.5. Flow Control
7. Recommended Clock Connections x
7.1. Driving Multiple Ports with the Same Clock 7.2. Alternate Clock Connections for MAC Async Client FIFO 7.3. F-Tile Clock Connections for PTP Synchronous and Asynchronous cases 7.4. Clock Connections for SyncE Operation 7.5. F-Tile PMA and FEC Direct PHY IP Clock Output
8. Register Descriptions x
8.1. Subsystem Registers 8.2. Port Registers 8.3. F-tile Address Maps 8.4. F-tile ANLT Port Register Map 8.5. F-tile PTP Tile Adapter Register Map
8.1. Subsystem Registers x
8.1.1. Device Feature Header Lo 8.1.2. Device Feature Header Hi 8.1.3. Feature GUID_L 8.1.4. Feature GUID_H 8.1.5. Feature CSR ADDR 8.1.6. Feature CSR Size Group 8.1.7. Version 8.1.8. Feature List 8.1.9. Interface Attribute Port X Parameters 8.1.10. HSSI Command/Status 8.1.11. HSSI Control/Address 8.1.12. HSSI Read Data 8.1.13. HSSI Write Data 8.1.14. HSSI Ethernet Port X Status
8.2. Port Registers x
8.2.1. E-Tile PTP Packet Classifier Registers
8.2.1. E-Tile PTP Packet Classifier Registers x
8.2.1.1. Recognized and Unrecognized Packet Counters 8.2.1.2. Parse Graph Specific Packet Counters
9. Ethernet SS IP Example Design x
9.1. Steps to Generate the Example Design 9.2. Supported Simulators 9.3. Running the Simulation Tests 9.4. Running the Hardware Tests
9.3. Running the Simulation Tests x
9.3.1. Steps to Simulate the Design Example
9.4. Running the Hardware Tests x
9.4.1. Supported Boards 9.4.2. Steps to Compile the Design Example for Hardware 9.4.3. Steps to Run the Design Example on Hardware
1. Introduction
2. Feature Description
3. Ethernet Subsystem Parameters
4. Subsystem Abstraction Layer (SAL)
5. Dynamic Reconfiguration Extension Subsystem
6. Interfaces and Signals
7. Recommended Clock Connections
8. Register Descriptions
9. Ethernet SS IP Example Design
10. Document Revision History for Ethernet Subsystem Intel FPGA IP User Guide: Early Access Customer Release

8.3. F-tile Address Maps

The following table shows the F-Tile Ethernet Reconfiguration Avalon® memory-mapped address ranges.
Table 35.  F-Tile Ethernet Reconfiguration Avalon® memory-mapped Address Ranges
Register Type Address Range
F-Tile AIB Config 0x0000 – 0x00FC
Soft CSRs 0x0100 – 0x0FFC
EHIP Registers 0x1000 – 0x5FFC
FEC/XCVRIF Registers 0x6000 – 0x9FFC

The Ethernet Reconfiguration interface provides access to the EHIP Avalon® memory-mapped address space for the local EHIP fracture, including MAC, PCS, FEC and XCVRIF, as well as soft CSRs implemented in the FPGA fabric. The layout of this register space is described in more detail in the F-tile Hard IP for Ethernet User Guide. All addresses in this section are byte addresses, although the registers described are always accessed on 32-bit boundaries.

The EHIP and FEC/XCVRIF Registers spaces are mapped differently for different ethernet modes (10g/25g, 50g, 40g/100g, 200g, 400g) and are described in the F-tile Hard IP for Ethernet User Guide.

Table 36.  F-tile Ethernet Base Address Ranges
Ethernet Mode eth_reconfig Base Address
10g/25g 0x1000
50g 0x2000
40g/100g 0x3000
200g 0x4000
400g 0x5000

The following table shows the F-tile CSR address (Section 8 in F-Tile Ethernet Intel® FPGA Hard IP User Guide) mapping for channel 0/Quad 0 FGT 0. The CSR address mapping for different channels share the same byte offset. For example, channel 0 base address starts at 0x020_0000, and channel 8 base address is 0x120_0000. You can directly add the CSR byte offset address with base address of the channel to obtain the CSR address on particular channel. The CSR address is in byte offset, so the offset is directly added to base address without multiplication. To access this register, you must write bits 2-25 of this calculated address to the HSSI Control/Address CSR with the set_csr SAL command.

Table 37.  F-tile CSR Address
Base Address Byte Offset Descriptions Configuration
Channel 0 (Quad 0 FGT 0) -
0x020_0000 (EHIP – Ethernet Reconfiguration) 0x0000 – 0x00FC F-Tile AIB Config -
0x0100 – 0x0FFC Soft CSRs
0x1000 (10GE/25GE) 0x000-0x07C PCS Configuration
0x080-0x1FC PCS Status
0x200-0x7FC MAC/PTP Configuration
0x800-0xFFC MAC/PTP Statistics
0x2000 (50GE) Same as above Same as above
0x3000 (40GE/100GE) Same as above Same as above
0x4000 (200GE) Same as above Same as above
0x5000 (400GE) Same as above Same as above
0x020_0000 (FEC/XCVR – Ethernet Reconfiguration) eth_reconfig Base Address Offset Address FEC/XCVRIF Lane Segment
0x6000 (25g) 0x000 - 0x0BC (Transceiver Interface Control ) segment 0
0x0C0 - 0x0FC (FEC Configuration )
0x100 - 0x13C (Transceiver Status)
0x140 - 0x1FC (FEC Status )
0x6200 (50g) Same as above segment 0
0x6400 (50g) Same as above segment 1
0x6600 (100g) Same as above segment 0
0x6800 (100g) Same as above segment 1
0x6A00 (100g) Same as above segment 2
0x6C00 (100g) Same as above segment 3
0x6E00 (200g) Same as above segment 0
0x7000 (200g) Same as above segment 1
0x7200 (200g) Same as above segment 2
0x7400 (200g) Same as above segment 3
0x7600 (200g) Same as above segment 4
0x7800 (200g) Same as above segment 5
0x7A00 (200g) Same as above segment 6
0x7C00 (200g) Same as above segment 7
0x7E00 (400g) Same as above segment 0
0x8000 (400g) Same as above segment 1
0x8200 (400g) Same as above segment 2
0x8400 (400g) Same as above segment 3
0x8600 (400g) Same as above segment 4
0x8800 (400g) Same as above segment 5
0x8A00 (400g) Same as above segment 6
0x8C00 (400g) Same as above segment 7
0x8E00 (400g) Same as above segment 8
0x9000 (400g) Same as above segment 9
0x9200 (400g) Same as above segment 10
0x9400 (400g) Same as above segment 11
0x9600 (400g) Same as above segment 12
0x9800 (400g) Same as above segment 13
0x9A00 (400g) Same as above segment 14
0x9C00 (400g) Same as above segment 15
0x020_A000 (Reserved) - Reserved -
0x021_1000 (PTP Packet Classifier) - PTP Packet Classifier -
0x024_0000 (PHY – XCVR Reconfiguration) - PHY – XCVR Reconfiguration -

The following example shows CSR access decoding.

Assuming you would like to access Tx MAC Link Fault Config register (For details, refer to F-tile Hard IP for Ethernet Register Map) for Agilex F-tile channel 8.

Tx MAC Link Fault Config register byte offset = 0x1200

F-tile transceiver channel 8 base address = 0x1200000

AXI-Lite CSR read request address = 0x405*4 + 0x1200000 = 0x1201014 (byte addressing)

This request will be decoded and routed to Ethernet Reconfiguration interface for processing.

Table 38.  Ethernet Reconfiguration Interface Register Base Addresses (F-tile)
Ethernet Mode FEC/XCVRIF Lane Segment eth_reconfig Base Address
25g s0 0x6000
50g s0 0x6200
s1 0x6400
100g s0 0x6600
s1 0x6800
s2 0x6A00
s3 0x6C00
200g s0 0x6E00
s1 0x7000
s2 0x7200
s3 0x7400
s4 0x7600
s5 0x7800
s6 0x7A00
s7 0x7C00
400g s0 0x7E00
s1 0x8000
s2 0x8200
s3 0x8400
s4 0x8600
s5 0x8800
s6 0x8A00
s7 0x8C00
s8 0x8E00
s9 0x9000
s10 0x9200
s11 0x9400
s12 0x9600
s13 0x9800
s14 0x9A00
s15 0x9C00
Related Information
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