High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP User Guide
ID
773264
Date
4/29/2024
Public
A newer version of this document is available. Customers should click here to go to the newest version.
Visible to Intel only — GUID: ydy1658418318663
Ixiasoft
1. About the High Bandwidth Memory (HBM2E) Interface Agilex™ 7 FPGA IP User Guide
2. Introduction to High Bandwidth Memory
3. Agilex™ 7 M-Series HBM2E Architecture
4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface FPGA IP
5. High Bandwidth Memory (HBM2E) Interface FPGA IP Interface
6. High Bandwidth Memory (HBM2E) Interface FPGA IP Performance
7. Debugging the High Bandwidth Memory (HBM2E) Interface FPGA IP
8. Document Revision History for High Bandwidth Memory (HBM2E) Interface FPGA IP User Guide
A. High Bandwidth Memory (HBM2E) Interface FPGA IP Quartus® Prime Software Flow
Visible to Intel only — GUID: ydy1658418318663
Ixiasoft
4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface FPGA IP
This chapter contains information on project creation, IP parameter descriptions, and pin planning for your High Bandwidth Memory (HBM2E) Interface FPGA IP.