External Memory Interfaces Agilex™ 7 M-Series FPGA IP Design Example User Guide

ID 772632
Date 7/08/2024
Public
Document Table of Contents

2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 7 M-Series FPGA IP

An automated design example flow is available for Agilex™ 7 M-Series external memory interfaces.

The Example Designs tab in the EMIF IP parameter editor allows you to set a variety of parameters to generate the synthesis and simulation design example file sets which you can use to validate your EMIF IP.

You can generate a design example that matches the Altera FPGA development kit, or for any EMIF IP that you generate. You can use the design example to assist your evaluation, or as a starting point for your own system.

Figure 1. General Design Example Workflows