2.3.6. Example: Byte Swizzling for Lockstep Configuration
Case A: DDR4 with sDQ[0]
sDQ[0] maps to the RUSER/WUSER group. It corresponds to the ECC lane in byte-swizzling notation. Because the BYTE_SWIZZLE_CH0 specification can only accept 0,1,2,3,ECC and X, the group number for other DQS groups must be reduced by 1.
This example illustrates the swizzling of DQS group 3 (BL0) with DQS group 2 (BL1), and DQS group 1 (BL2) with DQS group 0 (BL3), respectively.
Scheme | BL0 | BL1 | BL2 | BL3 | BL4 | BL5 | BL6 | BL7 |
---|---|---|---|---|---|---|---|---|
DDR4/5_AC_TOP | DQ[4] | DQ[3] | DQ[2] | DQ[1] | AC1 | Ac2 | AC0 | sDQ[0] |
DQS group number in byte swizzling notation | 3 | 2 | 1 | 0 | X | X | X | ECC |
After Byte Swizzling | 2 | 3 | 0 | 1 | X | X | X | ECC |
To achieve the swizzling described in the above table, enter the following BYTE_SWIZZLE_CH0 specification in User Extra Parameters:
BYTE_SWIZZLE_CH0=2,3,0,1,X,X,X,ECC;The method to swizzle the DQ pin within a group is the same for lockstep and non-lockstep configuration. Refer to the DQ Pin Swizzling Within DQS group for x32 DDR4 interface example for more information on how to configure DQ Pin Swizzling.
Case B: DDR4 with sDQ[4]
sDQ[4] maps to RUSER/WUSER group. It corresponds to the ECC lane in byte-swizzling notation.
Scheme | BL0 | BL1 | BL2 | BL3 | BL4 | BL5 | BL6 | BL7 |
---|---|---|---|---|---|---|---|---|
DDR4/5_AC_BOT | DQ[0] | AC0 | AC1 | AC2 | DQ[1] | DQ[2] | DQ[3] | sDQ[4] |
DQS group number in byte swizzling notation | 0 | X | X | X | 1 | 2 | 3 | ECC |
After Byte Swizzling | 1 | X | X | X | 0 | 3 | 2 | ECC |
This example illustrates the swizzling of DQS group 0 (BL0) with DQS group 1 (BL4), and DQS group 2 (BL5) with DQS group 3 (BL6), respectively.
To achieve this swizzling, enter the following BYTE SWIZZLE CH0 specification in User Extra Parameters:
BYTE_SWIZZLE_CH0=1,X,X,X,0,3,2,ECC;The method to swizzle the DQ pin within a group is the same for lockstep and non-lockstep configurations. For more information on how to configure DQ pin swizzling, refer to the DQ Pin Swizzling Within DQS group for x32 DDR4 interface example.
Case C: DDR4 x72 Lockstep Implemented with AC Pri Top Sub-Bank / Sec DQ Bot
sDQ[0] maps to RUSER/WUSER group. It corresponds to the ECC lane in byte-swizzling notation.
BL0 | BL1 | BL2 | BL3 | BL4 | BL5 | BL6 | BL7 | |
---|---|---|---|---|---|---|---|---|
Primary | ||||||||
Default Placement | DQ[4] | DQ[3] | DQ[2] | DQ[1] | AC1 | AC2 | AC0 | sDQ[0] |
DQS group number in byte swizzling notation | 3 | 2 | 1 | 0 | X | X | X | ECC |
After Byte Swizzling | 3 | 2 | 0 | 1 | X | X | X | ECC |
Secondary | ||||||||
Default Placement | DQ[8] | DQ[7] | DQ[6] | DQ[5] | GPIO | GPIO | GPIO | GPIO |
DQS group number in byte swizzling notation | 7 | 6 | 5 | 4 | X | X | X | X |
After Byte Swizzling | 6 | 7 | 4 | 5 | X | X | X | X |
In the above table, the After Byte Swizzling rows denote the DQS group implemented in the lane after the swizzling. To achieve the swizzling, enter the following parameter in User Extra Parameters:
BYTE_SWIZZLE_PRI=3,2,0,1,X,X,X,ECC; BYTE_SWIZZLE_SEC=6,7,4,5,X,X,X,X;
As this configuration is implemented using two IO96 banks, and the ECC lane is placed on the primary IO96 bank, specify the pin swizzling information for the ECC lane using PIN_SWIZZLE_PRI_ECC, if you want to swizzle the DQ pins within the ECC lane.
Case D: DDR4 x72 Lockstep Implemented with AC Pri Bot Sub-Bank / Sec DQ Bot
BL0 | BL1 | BL2 | BL3 | BL4 | BL5 | BL6 | BL7 | |
---|---|---|---|---|---|---|---|---|
Primary | ||||||||
Default Placement | DQ[0] | AC0 | AC1 | AC2 | DQ[1] | DQ[2] | DQ[3] | sDQ[4] |
DQS group number in byte swizzling notation | 0 | X | X | X | 1 | 2 | 3 | ECC |
After Byte Swizzling | 0 | X | X | X | 1 | 3 | 2 | ECC |
Secondary | ||||||||
Default Placement | DQ8 | DQ7 | DQ6 | DQ5 | GPIO | GPIO | GPIO | GPIO |
DQS group number in byte swizzling notation | 7 | 6 | 5 | 4 | X | X | X | X |
After Byte Swizzling | 7 | 6 | 4 | 5 | X | X | X | X |
In the above table, the After Byte Swizzling rows denote the DQS group implemented in the lane after the swizzling. To achieve the swizzling, enter the following parameter in User Extra Parameters:
BYTE_SWIZZLE_PRI=0,X,X,X,1,3,2,ECC; BYTE_SWIZZLE_SEC=7,6,4,5,X,X,X,X;
As this configuration is implemented using two IO96 banks, and the ECC lane is placed on the primary IO96 bank, specify the pin swizzling information for the ECC lane using PIN_SWIZZLE_PRI_ECC, if you want to swizzle the DQ pins within the ECC lane.
Case E: DDR4 x72 Lockstep Implemented with AC Pri Top Sub-Bank / Sec DQ Bot(m)
BL0 | BL1 | BL2 | BL3 | BL4 | BL5 | BL6 | BL7 | |
---|---|---|---|---|---|---|---|---|
Primary | ||||||||
Default Placement | DQ[3] | DQ[2] | DQ[1] | DQ[0] | AC1 | AC2 | AC0 | AC3 |
DQS group number in byte swizzling notation | 3 | 2 | 1 | 0 | X | X | X | X |
After Byte Swizzling | 2 | 3 | 0 | 1 | X | X | X | X |
Secondary | ||||||||
Default Placement | DQ[8] | DQ[7] | DQ[6] | DQ[5] | X | X | GPIO | sDQ[4] |
DQS group number in byte swizzling notation | 7 | 6 | 5 | 4 | X | X | X | ECC |
After Byte Swizzling | 4 | 5 | 6 | 7 | X | X | X | ECC |
In the above table, the After Byte Swizzling rows denote the DQS group implemented in the lane after the swizzling. To achieve the swizzling, enter the following parameter in User Extra Parameters:
BYTE_SWIZZLE_PRI=2,3,0,1,X,X,X,X; BYTE_SWIZZLE_SEC=4,5,6,7,X,X,X,ECC;
As this configuration is implemented using two IO96 banks, and the ECC lane is placed on the secondary IO96 bank, specify the pin swizzling information for the ECC lane using PIN_SWIZZLE_SEC_ECC, if you want to swizzle the DQ pins within the ECC lane.
Case F: DDR4 x64 Lockstep SODIMM (with x4 Memory Component) Implemented with AC Pri Top Sub-Bank / Sec DQ Bot
BL0 | BL1 | BL2 | BL3 | BL4 | BL5 | BL6 | BL7 | |
---|---|---|---|---|---|---|---|---|
Primary | ||||||||
Default Placement | DQ0 | DQ3 | DQ2 | DQ1 | AC1 | AC2 | AC0 | X |
DQS bundle in byte swizzling notation | 3 | 2 | 1 | 0 | X | X | X | X |
After Byte Swizzling | 2 | 3 | 0 | 1 | X | X | X | X |
Secondary | ||||||||
Default Placement | DQ7 | DQ6 | DQ5 | DQ4 | X | X | X | X |
DQS bundle in byte swizzling notation | 7 | 6 | 5 | 4 | X | X | X | X |
After Byte Swizzling | 7 | 6 | 5 | 4 | X | X | X | X |
In the above table, the After Byte Swizzling rows denote the DQS bundle implemented in the lane after the swizzling. To achieve the swizzling in the primary IO96 bank, enter the following parameter in User Extra Parameters:
BYTE_SWIZZLE_PRI= 2,3,0,1,X,X,X,X;
For x4 device widths, the values in BYTE_SWIZZLE represent the bundles of 2 x4 DQS groups. The lower DQS group of the bundle is connected to the lower half of the byte lane, while the upper DQS group of the bundle is connected to the upper half of the byte lane.
The placement of each DQS bundle and DQS group in this example, after the byte swizzling, follows the pattern shown below:
- CH0 Bundle 0 is placed on BL2 in the Primary IO96
- CH0 DQS0 connected to lower half of BL2
- CH0 DQS1 connected to upper half of BL2
- CH0 Bundle 1 is placed on BL3 in the Primary IO96
- CH0 DQS2 connected to lower half of BL3
- CH0 DQS3 connected to upper half of BL3
- CH0 Bundle 2 is placed on BL0 in the Primary IO96
- CH0 DQS4 connected to lower half of BL0
- CH0 DQS5 connected to upper half of BL0
- CH0 Bundle 3 is placed on BL1 in the Primary IO96
- CH0 DQS6 connected to lower half of BL1
- CH0 DQS7 connected to upper half of BL1
- CH0 Bundle 4 is placed on BL3 in the Secondary IO96
- CH0 DQS8 connected to lower half of BL3
- CH0 DQS9 connected to upper half of BL3
In this case, only four values are required to specify the pin swizzling information for a x4 DQS group.
Example:
- PIN_SWIZZLE_PRI_DQS0=3,2,0,1;
- PIN_SWIZZLE_PRI_DQS1=7,6,5,4;
- PIN_SWIZZLE_PRI_DQS6=24,25,26,27;
- PIN_SWIZZLE_PRI_DQS7=28,29,30,31;
- PIN_SWIZZLE_SEC_DQS14=59,57,58,56;
- PIN_SWIZZLE_SEC_DQS15=63,60,61,62;