External Memory Interfaces Agilex™ 7 M-Series FPGA IP Design Example User Guide

ID 772632
Date 7/08/2024
Public
Document Table of Contents

2.1.1.3.4. Guidelines for Selecting the DDR5 DRAM Component Package Type

For DDR5 discrete components, the Agilex™ 7 M-Series DDR5 IP supports:

  • 1 die per component, with either 1 or 2 ranks.

For DDR5 SODIMM and UDIMM, the Agilex™ 7 M-Series DDR5 IP supports 1 DIMM per channel with either 1 or 2 ranks.