External Memory Interfaces Agilex™ 7 M-Series FPGA IP Design Example User Guide

ID 772632
Date 7/08/2024
Public
Document Table of Contents

4. Document Revision History for External Memory Interfaces Agilex™ 7 M-Series FPGA IP Design Example User Guide

Document Version Quartus® Prime Version IP Version Changes
2024.07.08 24.2 6.2.0
  • In the Quick Start chapter, added the Example: Swizzling for a 2Ch x32 + ECC interface topic.
  • Implemented minor editorial improvements and branding changes throughout.
2024.04.01 24.1 6.1.0
  • In the Quick Start chapter:
    • Updated figures in several topics.
    • Modified the table in the Agilex™ 7 M-Series EMIF Parameter Editor Guidelines topic.
    • Added Using the EMIF Design Example with the Test Engine IP topic.
2023.12.04 23.4 6.0.0
  • In the Quick Start chapter:
    • Added Command-Address Mirroring to the Intel Agilex® 7 M-Series EMIF Parameter Editor Guidelines topic.
    • Added Generating the EMIF Design Example with the Performance Monitor topic.
2023.10.02 23.3 5.0.0
  • In the Quick Start chapter, modified the Configuring DQ Pin Swizzling section.
  • Updated several figures throughout.
2023.06.26 23.2 4.0.0 In the Quick Start chapter, made updates to figures and corrections to syntax examples in the Configuring DQ Pin Swizzling topic.
2023.04.03 23.1 3.0.0 Initial release.