Parameterizable Macros for Intel® FPGAs User Guide

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ID 772350
Date 10/02/2023
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Parameterizable Macros for Intel FPGAs Overview 3. Dual-Port Random Access Memory (RAM) Parameterizable Macros 4. FIFO Parameterizable Macros 5. I/O PLL Parameterizable Macros 6. CDC Parameterizable Macros 7. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide 8. Parameterizable Macros for Intel FPGAs User Guide Archives
2. Parameterizable Macros for Intel FPGAs Overview x
2.1. Available Parameterizable Macros for Intel FPGAs 2.2. Inserting HDL Code from Parameterizable Macro Templates
3. Dual-Port Random Access Memory (RAM) Parameterizable Macros x
3.1. Simple Dual-Port RAM Parameterizable Macro (simple_dual_port_ram) 3.2. True Dual-Port RAM Parameterizable Macro (true_dual_port_ram)
3.1. Simple Dual-Port RAM Parameterizable Macro (simple_dual_port_ram) x
3.1.1. Simple Dual-Port RAM Parameterizable Macro Port Descriptions 3.1.2. Simple Dual-Port RAM Parameterizable Macro Parameters 3.1.3. Simple Dual-Port RAM VHDL Instantiation Template 3.1.4. Simple Dual-Port RAM Verilog Instantiation Template 3.1.5. Simple Dual-Port RAM SystemVerilog Instantiation Template
3.2. True Dual-Port RAM Parameterizable Macro (true_dual_port_ram) x
3.2.1. True Dual-Port RAM Parameterizable Macro Port Descriptions 3.2.2. True Dual-Port RAM Parameterizable Macro Parameters 3.2.3. True Dual-Port RAM VHDL Instantiation Template True Dual-Port RAM VHDL Instantiation Template 3.2.4. True Dual-Port RAM Verilog Instantiation Template 3.2.5. True Dual-Port RAM SystemVerilog Instantiation Template
4. FIFO Parameterizable Macros x
4.1. Synchronous FIFO Parameterizable Macro (sync_fifo) 4.2. Asynchronous FIFO Parameterizable Macro (async_fifo)
4.1. Synchronous FIFO Parameterizable Macro (sync_fifo) x
4.1.1. Synchronous FIFO Parameterizable Macro Port Descriptions 4.1.2. Synchronous FIFO Parameterizable Macro Parameters 4.1.3. Synchronous FIFO VHDL Instantiation Template 4.1.4. Synchronous FIFO Verilog Instantiation Template 4.1.5. Synchronous FIFO SystemVerilog Instantiation Template
4.2. Asynchronous FIFO Parameterizable Macro (async_fifo) x
4.2.1. Asynchronous FIFO Parameterizable Macro Port Descriptions 4.2.2. Asynchronous FIFO Parameterizable Macro Parameters 4.2.3. Asynchronous FIFO VHDL Instantiation Template 4.2.4. Asynchronous FIFO Verilog Instantiation Template 4.2.5. Asynchronous FIFO SystemVerilog Instantiation Template
5. I/O PLL Parameterizable Macros x
5.1. I/O PLL Parameterizable Macro Port Descriptions 5.2. I/O PLL Parameterizable Macro Parameters 5.3. Basic I/O PLL VHDL Instantiation Template 5.4. Basic I/O PLL Verilog Instantiation Template 5.5. Basic I/O PLL SystemVerilog Instantiation Template
6. CDC Parameterizable Macros x
6.1. Synchronous Reset Synchronizer Parameterizable Macro (ipm_cdc_sync_rst) 6.2. Asynchronous Reset Synchronizer Parameterizable Macro (ipm_cdc_async_rst) 6.3. Synchronizer Using Single Clock Parameterizable Macro (ipm_cdc_1clk_sync) 6.4. Synchronizer Using Two Clocks Parameterizable Macro (ipm_cdc_2clks_sync) 6.5. Glitchless Clock MUX Parameterizable Macro (ipm_cdc_glitchless_clk_mux) 6.6. Bus Synchronizer Parameterizable Macro (ipm_cdc_bus_sync)
6.1. Synchronous Reset Synchronizer Parameterizable Macro (ipm_cdc_sync_rst) x
6.1.1. Synchronous Reset Synchronizer Parameterizable Macro Port Descriptions 6.1.2. Synchronous Reset Synchronizer Parameterizable Macro Parameters 6.1.3. Synchronous Reset Synchronizer VHDL Instantiation Template 6.1.4. Synchronous Reset Synchronizer Verilog Instantiation Template 6.1.5. Synchronous Reset Synchronizer SystemVerilog Instantiation Template
6.2. Asynchronous Reset Synchronizer Parameterizable Macro (ipm_cdc_async_rst) x
6.2.1. Asynchronous Reset Synchronizer Parameterizable Macro Port Descriptions 6.2.2. Asynchronous Reset Synchronizer Parameterizable Macro Parameters 6.2.3. Asynchronous Reset Synchronizer VHDL Instantiation Template 6.2.4. Asynchronous Reset Synchronizer Verilog Instantiation Template 6.2.5. Asynchronous Reset Synchronizer SystemVerilog Instantiation Template
6.3. Synchronizer Using Single Clock Parameterizable Macro (ipm_cdc_1clk_sync) x
6.3.1. Synchronizer Using Single Clock Parameterizable Macro Port Descriptions 6.3.2. Synchronizer Using Single Clock Parameterizable Macro Parameters 6.3.3. Synchronizer Using Single Clock VHDL Instantiation Template 6.3.4. Synchronizer Using Single Clock Verilog Instantiation Template 6.3.5. Synchronizer Using Single Clock SystemVerilog Instantiation Template
6.4. Synchronizer Using Two Clocks Parameterizable Macro (ipm_cdc_2clks_sync) x
6.4.1. Synchronizer Using Two Clocks Parameterizable Macro Port Descriptions 6.4.2. Synchronizer Using Two Clocks Parameterizable Macro Parameters 6.4.3. Synchronizer Using Two Clocks VHDL Instantiation Template 6.4.4. Synchronizer Using Two Clocks Verilog Instantiation Template 6.4.5. Synchronizer Using Two Clocks SystemVerilog Instantiation Template
6.5. Glitchless Clock MUX Parameterizable Macro (ipm_cdc_glitchless_clk_mux) x
6.5.1. Glitchless Clock MUX Parameterizable Macro Port Descriptions 6.5.2. Glitchless Clock MUX Parameterizable Macro Parameters 6.5.3. Glitchless Clock MUX VHDL Instantiation Template 6.5.4. Glitchless Clock MUX Verilog Instantiation Template 6.5.5. Glitchless Clock MUX SystemVerilog Instantiation Template
6.6. Bus Synchronizer Parameterizable Macro (ipm_cdc_bus_sync) x
6.6.1. Bus Synchronizer Parameterizable Macro Port Descriptions 6.6.2. Bus Synchronizer Parameterizable Macro Parameters 6.6.3. Bus Synchronizer VHDL Instantiation Template 6.6.4. Bus Synchronizer Verilog Instantiation Template 6.6.5. Bus Synchronizer SystemVerilog Instantiation Template
1. Answers to Top FAQs
2. Parameterizable Macros for Intel FPGAs Overview
3. Dual-Port Random Access Memory (RAM) Parameterizable Macros
4. FIFO Parameterizable Macros
5. I/O PLL Parameterizable Macros
6. CDC Parameterizable Macros
7. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide
8. Parameterizable Macros for Intel FPGAs User Guide Archives

3.2.3. True Dual-Port RAM VHDL Instantiation Template

True Dual-Port RAM VHDL Instantiation Template

-- Documentation :
-- https://www.intel.com/content/www/us/en/docs/programmable/772350/
-- Macro Location :
-- $QUARTUS_ROOTDIR/eda/sim_lib/altera_lnsim_components.vhd
-- Add the library and use clauses before the design unit declaration
library altera_lnsim; 
use altera_lnsim.altera_lnsim_components.all; 
-- Instantiating TRUE_DUAL_PORT_RAM
 <instance_name> : TRUE_DUAL_PORT_RAM
  generic map (
   -- Port A Parameters
    DATA_WIDTH_A =>                              8,
    ADDR_WIDTH_A =>                              11,
    BYTE_EN_WIDTH_A =>                           1,
    OUT_DATA_REG_CLK_A =>                        "UNREGISTERED",
    OUT_DATA_ACLR_A =>                           "NONE",
    OUT_DATA_SCLR_A =>                           "NONE",
    READ_DURING_WRITE_MODE_A =>                  "NEW_DATA_NO_NBE_READ",
    IN_CLK_EN_A =>                               "NORMAL",
    OUT_CLK_EN_A =>                              "NORMAL",
   -- Port B Parameters
    DATA_WIDTH_B =>                              8,
    ADDR_WIDTH_B =>                              11,
    BYTE_EN_WIDTH_B =>                           1,
    OUT_DATA_REG_CLK_B =>                        "UNREGISTERED",
    OUT_DATA_ACLR_B =>                           "NONE",
    OUT_DATA_SCLR_B =>                           "NONE",
    READ_DURING_WRITE_MODE_B =>                  "NEW_DATA_NO_NBE_READ",
    IN_CLK_EN_B =>                               "NORMAL",
    OUT_CLK_EN_B =>                              "NORMAL",
   -- Parameters common for Port A and Port B
    BYTE_SIZE =>                                 8,
    INIT_FILE =>                                 "",
    INIT_FILE_LAYOUT =>                          "PORT_A",
    MAX_DEPTH =>                                 2048
       )
port map ( 
 clock0 =>    _connected_to_clock0_,    -- input, width = 1   
 clock1 =>    _connected_to_clock1_,    -- input, width = 1   
 clocken0 =>  _connected_to_clocken0_,  -- input, width = 1   
 clocken1 =>  _connected_to_clocken1_,  -- input, width = 1     
 aclr =>      _connected_to_aclr_,      -- input, width = 1     
 sclr =>      _connected_to_sclr_,      -- input, width = 1   
 data_a =>    _connected_to_data_a_,    -- input, width = DATA_WIDTH_A  
 address_a => _connected_to_address_a_, -- input, width = ADDR_WIDTH_A  
 wren_a =>    _connected_to_wren_a_,    -- input, width = 1
 rden_a =>    _connected_to_rden_a_,    -- input, width = 1
 byteena_a => _connected_to_byteena_a_, -- input, width = BYTE_EN_WIDTH_A
 data_b =>    _connected_to_data_b_,    -- input, width = DATA_WIDTH_B
 address_b => _connected_to_address_b_, -- input, width = ADDR_WIDTH_B
 wren_b =>    _connected_to_wren_b_,    -- input, width = 1
 rden_b =>    _connected_to_rden_b_,    -- input, width = 1
 byteena_b => _connected_to_byteena_b_, -- input, width = BYTE_EN_WIDTH_B
 q_a =>       _connected_to_q_a_,       -- output, width = DATA_WIDTH_A  
 q_b =>       _connected_to_q_b_        -- output, width = DATA_WIDTH_B
);
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