Parameterizable Macros for Intel® FPGAs User Guide

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ID 772350
Date 10/02/2023
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Parameterizable Macros for Intel FPGAs Overview 3. Dual-Port Random Access Memory (RAM) Parameterizable Macros 4. FIFO Parameterizable Macros 5. I/O PLL Parameterizable Macros 6. CDC Parameterizable Macros 7. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide 8. Parameterizable Macros for Intel FPGAs User Guide Archives
2. Parameterizable Macros for Intel FPGAs Overview x
2.1. Available Parameterizable Macros for Intel FPGAs 2.2. Inserting HDL Code from Parameterizable Macro Templates
3. Dual-Port Random Access Memory (RAM) Parameterizable Macros x
3.1. Simple Dual-Port RAM Parameterizable Macro (simple_dual_port_ram) 3.2. True Dual-Port RAM Parameterizable Macro (true_dual_port_ram)
3.1. Simple Dual-Port RAM Parameterizable Macro (simple_dual_port_ram) x
3.1.1. Simple Dual-Port RAM Parameterizable Macro Port Descriptions 3.1.2. Simple Dual-Port RAM Parameterizable Macro Parameters 3.1.3. Simple Dual-Port RAM VHDL Instantiation Template 3.1.4. Simple Dual-Port RAM Verilog Instantiation Template 3.1.5. Simple Dual-Port RAM SystemVerilog Instantiation Template
3.2. True Dual-Port RAM Parameterizable Macro (true_dual_port_ram) x
3.2.1. True Dual-Port RAM Parameterizable Macro Port Descriptions 3.2.2. True Dual-Port RAM Parameterizable Macro Parameters 3.2.3. True Dual-Port RAM VHDL Instantiation Template 3.2.4. True Dual-Port RAM Verilog Instantiation Template 3.2.5. True Dual-Port RAM SystemVerilog Instantiation Template
4. FIFO Parameterizable Macros x
4.1. Synchronous FIFO Parameterizable Macro (sync_fifo) 4.2. Asynchronous FIFO Parameterizable Macro (async_fifo)
4.1. Synchronous FIFO Parameterizable Macro (sync_fifo) x
4.1.1. Synchronous FIFO Parameterizable Macro Port Descriptions 4.1.2. Synchronous FIFO Parameterizable Macro Parameters 4.1.3. Synchronous FIFO VHDL Instantiation Template 4.1.4. Synchronous FIFO Verilog Instantiation Template 4.1.5. Synchronous FIFO SystemVerilog Instantiation Template
4.2. Asynchronous FIFO Parameterizable Macro (async_fifo) x
4.2.1. Asynchronous FIFO Parameterizable Macro Port Descriptions 4.2.2. Asynchronous FIFO Parameterizable Macro Parameters 4.2.3. Asynchronous FIFO VHDL Instantiation Template 4.2.4. Asynchronous FIFO Verilog Instantiation Template 4.2.5. Asynchronous FIFO SystemVerilog Instantiation Template
5. I/O PLL Parameterizable Macros x
5.1. I/O PLL Parameterizable Macro Port Descriptions 5.2. I/O PLL Parameterizable Macro Parameters 5.3. Basic I/O PLL VHDL Instantiation Template 5.4. Basic I/O PLL Verilog Instantiation Template 5.5. Basic I/O PLL SystemVerilog Instantiation Template
6. CDC Parameterizable Macros x
6.1. Synchronous Reset Synchronizer Parameterizable Macro (ipm_cdc_sync_rst) 6.2. Asynchronous Reset Synchronizer Parameterizable Macro (ipm_cdc_async_rst) 6.3. Synchronizer Using Single Clock Parameterizable Macro (ipm_cdc_1clk_sync) 6.4. Synchronizer Using Two Clocks Parameterizable Macro (ipm_cdc_2clks_sync) 6.5. Glitchless Clock MUX Parameterizable Macro (ipm_cdc_glitchless_clk_mux) 6.6. Bus Synchronizer Parameterizable Macro (ipm_cdc_bus_sync)
6.1. Synchronous Reset Synchronizer Parameterizable Macro (ipm_cdc_sync_rst) x
6.1.1. Synchronous Reset Synchronizer Parameterizable Macro Port Descriptions 6.1.2. Synchronous Reset Synchronizer Parameterizable Macro Parameters 6.1.3. Synchronous Reset Synchronizer VHDL Instantiation Template 6.1.4. Synchronous Reset Synchronizer Verilog Instantiation Template 6.1.5. Synchronous Reset Synchronizer SystemVerilog Instantiation Template
6.2. Asynchronous Reset Synchronizer Parameterizable Macro (ipm_cdc_async_rst) x
6.2.1. Asynchronous Reset Synchronizer Parameterizable Macro Port Descriptions 6.2.2. Asynchronous Reset Synchronizer Parameterizable Macro Parameters 6.2.3. Asynchronous Reset Synchronizer VHDL Instantiation Template 6.2.4. Asynchronous Reset Synchronizer Verilog Instantiation Template 6.2.5. Asynchronous Reset Synchronizer SystemVerilog Instantiation Template
6.3. Synchronizer Using Single Clock Parameterizable Macro (ipm_cdc_1clk_sync) x
6.3.1. Synchronizer Using Single Clock Parameterizable Macro Port Descriptions 6.3.2. Synchronizer Using Single Clock Parameterizable Macro Parameters 6.3.3. Synchronizer Using Single Clock VHDL Instantiation Template 6.3.4. Synchronizer Using Single Clock Verilog Instantiation Template 6.3.5. Synchronizer Using Single Clock SystemVerilog Instantiation Template
6.4. Synchronizer Using Two Clocks Parameterizable Macro (ipm_cdc_2clks_sync) x
6.4.1. Synchronizer Using Two Clocks Parameterizable Macro Port Descriptions 6.4.2. Synchronizer Using Two Clocks Parameterizable Macro Parameters 6.4.3. Synchronizer Using Two Clocks VHDL Instantiation Template 6.4.4. Synchronizer Using Two Clocks Verilog Instantiation Template 6.4.5. Synchronizer Using Two Clocks SystemVerilog Instantiation Template
6.5. Glitchless Clock MUX Parameterizable Macro (ipm_cdc_glitchless_clk_mux) x
6.5.1. Glitchless Clock MUX Parameterizable Macro Port Descriptions 6.5.2. Glitchless Clock MUX Parameterizable Macro Parameters 6.5.3. Glitchless Clock MUX VHDL Instantiation Template 6.5.4. Glitchless Clock MUX Verilog Instantiation Template 6.5.5. Glitchless Clock MUX SystemVerilog Instantiation Template
6.6. Bus Synchronizer Parameterizable Macro (ipm_cdc_bus_sync) x
6.6.1. Bus Synchronizer Parameterizable Macro Port Descriptions 6.6.2. Bus Synchronizer Parameterizable Macro Parameters 6.6.3. Bus Synchronizer VHDL Instantiation Template 6.6.4. Bus Synchronizer Verilog Instantiation Template 6.6.5. Bus Synchronizer SystemVerilog Instantiation Template
1. Answers to Top FAQs
2. Parameterizable Macros for Intel FPGAs Overview
3. Dual-Port Random Access Memory (RAM) Parameterizable Macros
4. FIFO Parameterizable Macros
5. I/O PLL Parameterizable Macros
6. CDC Parameterizable Macros
7. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide
8. Parameterizable Macros for Intel FPGAs User Guide Archives

3.2.1. True Dual-Port RAM Parameterizable Macro Port Descriptions

Table 3.  True Dual-Port RAM Parameterizable Macro Port Descriptions
Port Type Required Description
clock0 Input Yes The following describes which memory clocks you must connect to the clock0 port, and the port synchronization in different clocking modes:
  • Single clock: Connect your single source clock to clock0 port. The same source clock synchronizes all registered ports.
  • Read/Write: Connect your read clock to clock0 port. The write clock synchronizes all registered ports related to write operation, such as data_a port, address_a port, wren_a port, and byteena_a port.
  • Input Output: Connect your input clock to clock0 port. The input clock synchronizes all registered input ports.
  • Independent clock: Connect your port A clock to clock0 port. The port A clock synchronizes all registered input and output ports of port A.
clock1 Input Optional The following describes which memory clocks you must connect to the clock1 port, and port synchronization in different clocking modes:
  • Single clock: Not applicable. The clock1 port synchronizes all registered ports.
  • Read/Write: Connect your read clock to clock1 port. The read clock synchronizes all registered ports related to read operation, such as address_b port and rden_b port.
  • Input Output: Connect your output clock to clock1 port. the output clock synchronizes all the registered output ports.
  • Independent clock: Connect your port B clock to clock1 port. The port B clock synchronizes all registered input and output ports of port B.
clocken0 Input Optional Clock enable input for clock0 port.
clocken1 Input Optional Clock enable input for clock1 port.
aclr Input Optional Asynchronous clear port which asynchronously clears the registered input data output port(s) clocked by clock0. You can control the effect of this port through the asynchronous clear parameters:
  • OUT_DATA_ACLR_A
  • OUT_DATA_ACLR_B
sclr Input Optional Synchronous clear port. Clears the registered data output ports.
data_a Input Yes Data input port at port A.
address_a Input Yes Address port at port A.
wren_a Input Optional (Always pull low if not connected) Write enable port at Port A.
rden_a Input Optional Read enable port for port A.
byteena_a Input Optional Byte enable port at Port A to mask the data_a port so that only specific bits of the data are written to the memory.
data_b Input Optional Data input port at port B.
address_b Input Optional Address port at port B.
wren_b Input Yes Write enable port at Port B.
rden_b Input Optional Read enable input for port B.
byteena_b Input Optional Byte enable port at Port B to mask the data_b port so that only specific bits of the data are written to the memory.
q_a Output Yes Data output port at port A. The width of q_a port must be equal to the width of data_a port.
q_b Output Yes Data output port at port B. The width of q_b port must be equal to the width of data_b port.
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