Parameterizable Macros for Intel® FPGAs User Guide

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Date 10/02/2023
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Parameterizable Macros for Intel FPGAs Overview 3. Dual-Port Random Access Memory (RAM) Parameterizable Macros 4. FIFO Parameterizable Macros 5. I/O PLL Parameterizable Macros 6. CDC Parameterizable Macros 7. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide 8. Parameterizable Macros for Intel FPGAs User Guide Archives
2. Parameterizable Macros for Intel FPGAs Overview x
2.1. Available Parameterizable Macros for Intel FPGAs 2.2. Inserting HDL Code from Parameterizable Macro Templates
3. Dual-Port Random Access Memory (RAM) Parameterizable Macros x
3.1. Simple Dual-Port RAM Parameterizable Macro (simple_dual_port_ram) 3.2. True Dual-Port RAM Parameterizable Macro (true_dual_port_ram)
3.1. Simple Dual-Port RAM Parameterizable Macro (simple_dual_port_ram) x
3.1.1. Simple Dual-Port RAM Parameterizable Macro Port Descriptions 3.1.2. Simple Dual-Port RAM Parameterizable Macro Parameters 3.1.3. Simple Dual-Port RAM VHDL Instantiation Template 3.1.4. Simple Dual-Port RAM Verilog Instantiation Template 3.1.5. Simple Dual-Port RAM SystemVerilog Instantiation Template
3.2. True Dual-Port RAM Parameterizable Macro (true_dual_port_ram) x
3.2.1. True Dual-Port RAM Parameterizable Macro Port Descriptions 3.2.2. True Dual-Port RAM Parameterizable Macro Parameters 3.2.3. True Dual-Port RAM VHDL Instantiation Template 3.2.4. True Dual-Port RAM Verilog Instantiation Template 3.2.5. True Dual-Port RAM SystemVerilog Instantiation Template
4. FIFO Parameterizable Macros x
4.1. Synchronous FIFO Parameterizable Macro (sync_fifo) 4.2. Asynchronous FIFO Parameterizable Macro (async_fifo)
4.1. Synchronous FIFO Parameterizable Macro (sync_fifo) x
4.1.1. Synchronous FIFO Parameterizable Macro Port Descriptions 4.1.2. Synchronous FIFO Parameterizable Macro Parameters 4.1.3. Synchronous FIFO VHDL Instantiation Template 4.1.4. Synchronous FIFO Verilog Instantiation Template 4.1.5. Synchronous FIFO SystemVerilog Instantiation Template
4.2. Asynchronous FIFO Parameterizable Macro (async_fifo) x
4.2.1. Asynchronous FIFO Parameterizable Macro Port Descriptions 4.2.2. Asynchronous FIFO Parameterizable Macro Parameters 4.2.3. Asynchronous FIFO VHDL Instantiation Template 4.2.4. Asynchronous FIFO Verilog Instantiation Template 4.2.5. Asynchronous FIFO SystemVerilog Instantiation Template
5. I/O PLL Parameterizable Macros x
5.1. I/O PLL Parameterizable Macro Port Descriptions 5.2. I/O PLL Parameterizable Macro Parameters 5.3. Basic I/O PLL VHDL Instantiation Template 5.4. Basic I/O PLL Verilog Instantiation Template 5.5. Basic I/O PLL SystemVerilog Instantiation Template
6. CDC Parameterizable Macros x
6.1. Synchronous Reset Synchronizer Parameterizable Macro (ipm_cdc_sync_rst) 6.2. Asynchronous Reset Synchronizer Parameterizable Macro (ipm_cdc_async_rst) 6.3. Synchronizer Using Single Clock Parameterizable Macro (ipm_cdc_1clk_sync) 6.4. Synchronizer Using Two Clocks Parameterizable Macro (ipm_cdc_2clks_sync) 6.5. Glitchless Clock MUX Parameterizable Macro (ipm_cdc_glitchless_clk_mux) 6.6. Bus Synchronizer Parameterizable Macro (ipm_cdc_bus_sync)
6.1. Synchronous Reset Synchronizer Parameterizable Macro (ipm_cdc_sync_rst) x
6.1.1. Synchronous Reset Synchronizer Parameterizable Macro Port Descriptions 6.1.2. Synchronous Reset Synchronizer Parameterizable Macro Parameters 6.1.3. Synchronous Reset Synchronizer VHDL Instantiation Template 6.1.4. Synchronous Reset Synchronizer Verilog Instantiation Template 6.1.5. Synchronous Reset Synchronizer SystemVerilog Instantiation Template
6.2. Asynchronous Reset Synchronizer Parameterizable Macro (ipm_cdc_async_rst) x
6.2.1. Asynchronous Reset Synchronizer Parameterizable Macro Port Descriptions 6.2.2. Asynchronous Reset Synchronizer Parameterizable Macro Parameters 6.2.3. Asynchronous Reset Synchronizer VHDL Instantiation Template 6.2.4. Asynchronous Reset Synchronizer Verilog Instantiation Template 6.2.5. Asynchronous Reset Synchronizer SystemVerilog Instantiation Template
6.3. Synchronizer Using Single Clock Parameterizable Macro (ipm_cdc_1clk_sync) x
6.3.1. Synchronizer Using Single Clock Parameterizable Macro Port Descriptions 6.3.2. Synchronizer Using Single Clock Parameterizable Macro Parameters 6.3.3. Synchronizer Using Single Clock VHDL Instantiation Template 6.3.4. Synchronizer Using Single Clock Verilog Instantiation Template 6.3.5. Synchronizer Using Single Clock SystemVerilog Instantiation Template
6.4. Synchronizer Using Two Clocks Parameterizable Macro (ipm_cdc_2clks_sync) x
6.4.1. Synchronizer Using Two Clocks Parameterizable Macro Port Descriptions 6.4.2. Synchronizer Using Two Clocks Parameterizable Macro Parameters 6.4.3. Synchronizer Using Two Clocks VHDL Instantiation Template 6.4.4. Synchronizer Using Two Clocks Verilog Instantiation Template 6.4.5. Synchronizer Using Two Clocks SystemVerilog Instantiation Template
6.5. Glitchless Clock MUX Parameterizable Macro (ipm_cdc_glitchless_clk_mux) x
6.5.1. Glitchless Clock MUX Parameterizable Macro Port Descriptions 6.5.2. Glitchless Clock MUX Parameterizable Macro Parameters 6.5.3. Glitchless Clock MUX VHDL Instantiation Template 6.5.4. Glitchless Clock MUX Verilog Instantiation Template 6.5.5. Glitchless Clock MUX SystemVerilog Instantiation Template
6.6. Bus Synchronizer Parameterizable Macro (ipm_cdc_bus_sync) x
6.6.1. Bus Synchronizer Parameterizable Macro Port Descriptions 6.6.2. Bus Synchronizer Parameterizable Macro Parameters 6.6.3. Bus Synchronizer VHDL Instantiation Template 6.6.4. Bus Synchronizer Verilog Instantiation Template 6.6.5. Bus Synchronizer SystemVerilog Instantiation Template
1. Answers to Top FAQs
2. Parameterizable Macros for Intel FPGAs Overview
3. Dual-Port Random Access Memory (RAM) Parameterizable Macros
4. FIFO Parameterizable Macros
5. I/O PLL Parameterizable Macros
6. CDC Parameterizable Macros
7. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide
8. Parameterizable Macros for Intel FPGAs User Guide Archives

6.5. Glitchless Clock MUX Parameterizable Macro (ipm_cdc_glitchless_clk_mux)

The glitchless clock MUX parameterizable macro (ipm_cdc_glitchless_clk_mux) supports designs with multi-frequency clocks. Such design commonly require switching the clock source while the design is running. You can implement this clock switching by multiplexing two different frequency clock sources in hardware and controlling the multiplexer select line with internal logic.

The two clock frequencies that you switch can be totally unrelated to each other, or they may be multiples of each other. In either case, there is a possibility of generating a glitch on the clock line at the time of the switch.

The glitchless clock mux macro allows you to avoid a glitch at the output of the clock line of a switch by specifying the relation of the input clocks with the CLK_TYPE parameter. Use the CLK_TYPE parameter to specify whether clocks are related (RELATED_CLKS) or unrelated (UNRELATED_CLKS).

Figure 11. Glitchless Clock Mux Parameterizable Macro Block Diagram



Section Content
Glitchless Clock MUX Parameterizable Macro Port Descriptions
Glitchless Clock MUX Parameterizable Macro Parameters
Glitchless Clock MUX VHDL Instantiation Template
Glitchless Clock MUX Verilog Instantiation Template
Glitchless Clock MUX SystemVerilog Instantiation Template

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