Parameterizable Macros for Intel® FPGAs User Guide

ID 772350
Date 10/02/2023
Public

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5.4. Basic I/O PLL Verilog Instantiation Template

Basic I/O PLL Verilog Instantiation Template

//Quartus Prime Parameterizable Macro Template
//IPM IOPLL BASIC
//Documentation :
//https://www.intel.com/content/www/us/en/docs/programmable/772350/
//Macro Location :
//$QUARTUS_ROOTDIR/libraries/megafunctions/ipm_iopll_basic.v

 ipm_iopll_basic #(
  .REFERENCE_CLOCK_FREQUENCY ("100.0 MHz"),
  .N_CNT                     (1),
  .M_CNT                     (6),
  .C0_CNT                    (1),
  .C1_CNT                    (1),
  .C2_CNT                    (1),
  .C3_CNT                    (1),
  .C4_CNT                    (1),
  .C5_CNT                    (1),
  .C6_CNT                    (1),
  .PLL_SIM_MODEL             ("")// It is a simulation specific parameter 
                                 // to select the technology dependent IOPLL 
                                 // simulation model. Allowed values are 
                                 // "Stratix 10", "Agilex 7 F-Series", 
                                 // "Agilex 7 (F-Series)", "Agilex 7 I-Series",
                                 // "Agilex 7 (I-Series)", "Agilex 7 M-Series", 
                                 // "Agilex 7 (M-Series)"
    ) <instance_name> (
    .refclk    (_connected_to_refclk_),      //input, width = 1
    .reset     (_connected_to_reset_),       //input, width = 1
    .outclk0   (_connected_to_outclk0_),     //output, width = 1
    .outclk1   (_connected_to_outclk1_),     //output, width = 1
    .outclk2   (_connected_to_outclk2_),     //output, width = 1
    .outclk3   (_connected_to_outclk3_),     //output, width = 1
    .outclk4   (_connected_to_outclk4_),     //output, width = 1
    .outclk5   (_connected_to_outclk5_),     //output, width = 1
    .outclk6   (_connected_to_outclk6_),     //output, width = 1
    .locked    (_connected_to_locked_)       //output, width = 1
	);