Parameterizable Macros for Intel® FPGAs User Guide

ID 772350
Date 10/02/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.3. Synchronizer Using Single Clock Parameterizable Macro (ipm_cdc_1clk_sync)

The synchronizer using single clock parameterizable macro (ipm_cdc_1clk_sync) synchronizes a one-bit signal with only one clock. You can use the macro for signals that do not have an associated clock. The number of the synchronizer stages is configurable, allowing a range from three to ten stages. You can also specify the initial value on the synchronization register, either 1 or 0 for simulation.

Figure 9. Synchronizer Using Single Clock Parameterizable Macro Block Diagram