Parameterizable Macros for Intel® FPGAs User Guide

ID 772350
Date 10/02/2023
Public

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6.4.3. Synchronizer Using Two Clocks VHDL Instantiation Template

Synchronizer Using Two Clocks VHDL Instantiation Template

-- Documentation :
-- https://www.intel.com/content/www/us/en/docs/programmable/772350/
-- Macro Location :
-- $QUARTUS_ROOTDIR/eda/sim_lib/altera_lnsim_components.vhd
-- Add the library and use clauses before the design unit declaration
library altera_lnsim; 
use altera_lnsim.altera_lnsim_components.all; 
-- Instantiating IPM_CDC_2CLKS_SYNC
   <instance_name> : IPM_CDC_2CLKS_SYNC
      generic map (
			INITIAL_VALUE =>     0,
			NUM_STAGES =>        3
			)
	     port map ( 
          src_clk =>   _connected_to_src_clk_,   -- input, width = 1  
          src_sig =>   _connected_to_src_sig_,   -- input, width = 1
          dst_clk =>   _connected_to_dst_clk_,   -- input, width = 1
          dst_sig =>   _connected_to_dst_sig_    -- output, width = 1
          );