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1. Answers to Top FAQs
2. Parameterizable Macros for Intel FPGAs Overview
3. Dual-Port Random Access Memory (RAM) Parameterizable Macros
4. FIFO Parameterizable Macros
5. I/O PLL Parameterizable Macros
6. CDC Parameterizable Macros
7. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide
8. Parameterizable Macros for Intel FPGAs User Guide Archives
3.1.1. Simple Dual-Port RAM Parameterizable Macro Port Descriptions
3.1.2. Simple Dual-Port RAM Parameterizable Macro Parameters
3.1.3. Simple Dual-Port RAM VHDL Instantiation Template
3.1.4. Simple Dual-Port RAM Verilog Instantiation Template
3.1.5. Simple Dual-Port RAM SystemVerilog Instantiation Template
6.1. Synchronous Reset Synchronizer Parameterizable Macro (ipm_cdc_sync_rst)
6.2. Asynchronous Reset Synchronizer Parameterizable Macro (ipm_cdc_async_rst)
6.3. Synchronizer Using Single Clock Parameterizable Macro (ipm_cdc_1clk_sync)
6.4. Synchronizer Using Two Clocks Parameterizable Macro (ipm_cdc_2clks_sync)
6.5. Glitchless Clock MUX Parameterizable Macro (ipm_cdc_glitchless_clk_mux)
6.6. Bus Synchronizer Parameterizable Macro (ipm_cdc_bus_sync)
6.1.1. Synchronous Reset Synchronizer Parameterizable Macro Port Descriptions
6.1.2. Synchronous Reset Synchronizer Parameterizable Macro Parameters
6.1.3. Synchronous Reset Synchronizer VHDL Instantiation Template
6.1.4. Synchronous Reset Synchronizer Verilog Instantiation Template
6.1.5. Synchronous Reset Synchronizer SystemVerilog Instantiation Template
6.2.1. Asynchronous Reset Synchronizer Parameterizable Macro Port Descriptions
6.2.2. Asynchronous Reset Synchronizer Parameterizable Macro Parameters
6.2.3. Asynchronous Reset Synchronizer VHDL Instantiation Template
6.2.4. Asynchronous Reset Synchronizer Verilog Instantiation Template
6.2.5. Asynchronous Reset Synchronizer SystemVerilog Instantiation Template
6.3.1. Synchronizer Using Single Clock Parameterizable Macro Port Descriptions
6.3.2. Synchronizer Using Single Clock Parameterizable Macro Parameters
6.3.3. Synchronizer Using Single Clock VHDL Instantiation Template
6.3.4. Synchronizer Using Single Clock Verilog Instantiation Template
6.3.5. Synchronizer Using Single Clock SystemVerilog Instantiation Template
6.4.1. Synchronizer Using Two Clocks Parameterizable Macro Port Descriptions
6.4.2. Synchronizer Using Two Clocks Parameterizable Macro Parameters
6.4.3. Synchronizer Using Two Clocks VHDL Instantiation Template
6.4.4. Synchronizer Using Two Clocks Verilog Instantiation Template
6.4.5. Synchronizer Using Two Clocks SystemVerilog Instantiation Template
6.5.1. Glitchless Clock MUX Parameterizable Macro Port Descriptions
6.5.2. Glitchless Clock MUX Parameterizable Macro Parameters
6.5.3. Glitchless Clock MUX VHDL Instantiation Template
6.5.4. Glitchless Clock MUX Verilog Instantiation Template
6.5.5. Glitchless Clock MUX SystemVerilog Instantiation Template
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4.1. Synchronous FIFO Parameterizable Macro (sync_fifo)
In the synchronous FIFO parameterizable macro (sync_fifo), the read and write signals are synchronized to the same clock. Memory used in this macro is simple dual port RAM.
Figure 4. Synchronous FIFO Parameterizable Macro Block Diagram
This section provides the block diagrams, port descriptions, parameter tables, and instantiation templates for this parameterizable macro.