Parameterizable Macros for Intel® FPGAs User Guide

ID 772350
Date 10/02/2023
Public

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6.3.4. Synchronizer Using Single Clock Verilog Instantiation Template

Synchronizer Using Single Clock Verilog Instantiation Template

//Quartus Prime Parameterizable Macro Template
//IPM_CDC_1CLK_SYNC
//Documentation :
//https://www.intel.com/content/www/us/en/docs/programmable/772350/
//Macro Location :
//$QUARTUS_ROOTDIR/libraries/megafunctions/ipm_cdc_1clk_sync.sv
	
   ipm_cdc_1clk_sync #(
      .INITIAL_VALUE                  (0),
	  .NUM_STAGES                     (3)
	) <instance_name> (
         .clk           (_connected_to_clk_),       //input, width = 1
         .async_in      (_connected_to_async_in_),  //input, width = 1
         .sync_out      (_connected_to_sync_out_)   //output, width = 1
	);