Parameterizable Macros for Intel FPGAs User Guide

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ID 772350
Date 6/26/2023
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Parameterizable Macros for Intel FPGAs Overview 3. Dual-Port Random Access Memory (RAM) Parameterizable Macros 4. FIFO Parameterizable Macros 5. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide 6. Parameterizable Macros for Intel FPGAs User Guide Archives
2. Parameterizable Macros for Intel FPGAs Overview x
2.1. Available Parameterizable Macros for Intel FPGAs 2.2. Inserting HDL Code from Parameterizable Macros Template
3. Dual-Port Random Access Memory (RAM) Parameterizable Macros x
3.1. Simple Dual-Port RAM Parameterizable Macros 3.2. True Dual-Port RAM Parameterizable Macros
3.1. Simple Dual-Port RAM Parameterizable Macros x
3.1.1. Simple Dual-Port RAM Port Descriptions 3.1.2. Simple Dual-Port RAM Parameters 3.1.3. Simple Dual-Port RAM VHDL Instantiation Template 3.1.4. Simple Dual-Port RAM Verilog Instantiation Template
3.2. True Dual-Port RAM Parameterizable Macros x
3.2.1. True Dual-Port RAM Port Descriptions 3.2.2. True Dual-Port RAM Parameters 3.2.3. True Dual-Port RAM VHDL Instantiation Template 3.2.4. True Dual-Port RAM Verilog Instantiation Template
4. FIFO Parameterizable Macros x
4.1. Asynchronous FIFO Parameterizable Macros 4.2. Synchronous FIFO Parameterizable Macros
4.1. Asynchronous FIFO Parameterizable Macros x
4.1.1. Asynchronous FIFO Port Descriptions 4.1.2. Asynchronous FIFO Parameters 4.1.3. Asynchronous FIFO VHDL Instantiation Template 4.1.4. Asynchronous FIFO Verilog Instantiation Template
4.2. Synchronous FIFO Parameterizable Macros x
4.2.1. Synchronous FIFO Port Descriptions 4.2.2. Synchronous FIFO Parameters 4.2.3. Synchronous FIFO VHDL Instantiation Template 4.2.4. Synchronous FIFO Verilog Instantiation Template
1. Answers to Top FAQs
2. Parameterizable Macros for Intel FPGAs Overview
3. Dual-Port Random Access Memory (RAM) Parameterizable Macros
4. FIFO Parameterizable Macros
5. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide
6. Parameterizable Macros for Intel FPGAs User Guide Archives

3.2. True Dual-Port RAM Parameterizable Macros

In True Dual-Port RAM mode, Port A and Port B are available with two address ports (one at Port A and one at Port B) and two data output ports (one at Port A and one at Port B). Both Port A and Port B can perform read and write operations according to the address provided from its address port. The same address is always referenced when read and write operations are happening at the same time at the same port.

Figure 3. True Dual-Port RAM Block Diagram



Section Content
True Dual-Port RAM Port Descriptions
True Dual-Port RAM Parameters
True Dual-Port RAM VHDL Instantiation Template
True Dual-Port RAM Verilog Instantiation Template

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