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1. Answers to Top FAQs
2. Parameterizable Macros for Intel FPGAs Overview
3. Dual-Port Random Access Memory (RAM) Parameterizable Macros
4. FIFO Parameterizable Macros
5. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide
6. Parameterizable Macros for Intel FPGAs User Guide Archives
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4.2.4. Synchronous FIFO Verilog Instantiation Template
SYNC_FIFO Verilog Instantiation Template
//Quartus Prime Parameterizable Macro Template //SYNC FIFO //Documentation : //https://www.intel.com/content/www/us/en/docs/programmable/772350/ //Macro Location : //$QUARTUS_ROOTDIR/libraries/megafunctions/sync_fifo.v sync_fifo #( .ADD_RAM_OUTPUT_REGISTER ("OFF"), .ALMOST_EMPTY_VALUE (1), .ALMOST_FULL_VALUE (1), .ENABLE_SCLR ("OFF"), .ENABLE_ACLR ("OFF"), .ALLOW_RWCYCLE_WHEN_FULL ("ON"), .ENABLE_SHOWAHEAD ("OFF"), .DATA_WIDTH (8), .ADDR_WIDTH (11), .OVERFLOW_CHECKING ("ON"), .UNDERFLOW_CHECKING ("ON"), .MAXIMUM_DEPTH (2048), .BYTE_SIZE (8), .BYTE_EN_WIDTH (1) ) <instance_name> ( .clock (_connected_to_clock_), //input, width = 1 .data (_connected_to_data_), //input, width = DATA_WIDTH .rdreq (_connected_to_rdreq_), //input, width = 1 .sclr (_connected_to_sclr_), //input, width = 1, synch reset .aclr (_connected_to_aclr_), //input, width = 1, asynch reset .wrreq (_connected_to_wrreq_), //input, width = 1 .byteena (_connected_to_byteena_), //input, width = BYTE_EN_WIDTH .almost_empty (_connected_to_almost_empty_), //output, width = 1 .almost_full (_connected_to_almost_full_), //output, width = 1 .q (_connected_to_q_), //output, width = DATA_WIDTH .usedw (_connected_to_usedw_), //output, width = ADDR_WIDTH .empty (_connected_to_empty_), //output, width = 1 .full (_connected_to_full_) //output, width = 1 );