Parameterizable Macros for Intel FPGAs User Guide

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ID 772350
Date 6/26/2023
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Parameterizable Macros for Intel FPGAs Overview 3. Dual-Port Random Access Memory (RAM) Parameterizable Macros 4. FIFO Parameterizable Macros 5. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide 6. Parameterizable Macros for Intel FPGAs User Guide Archives
2. Parameterizable Macros for Intel FPGAs Overview x
2.1. Available Parameterizable Macros for Intel FPGAs 2.2. Inserting HDL Code from Parameterizable Macros Template
3. Dual-Port Random Access Memory (RAM) Parameterizable Macros x
3.1. Simple Dual-Port RAM Parameterizable Macros 3.2. True Dual-Port RAM Parameterizable Macros
3.1. Simple Dual-Port RAM Parameterizable Macros x
3.1.1. Simple Dual-Port RAM Port Descriptions 3.1.2. Simple Dual-Port RAM Parameters 3.1.3. Simple Dual-Port RAM VHDL Instantiation Template 3.1.4. Simple Dual-Port RAM Verilog Instantiation Template
3.2. True Dual-Port RAM Parameterizable Macros x
3.2.1. True Dual-Port RAM Port Descriptions 3.2.2. True Dual-Port RAM Parameters 3.2.3. True Dual-Port RAM VHDL Instantiation Template 3.2.4. True Dual-Port RAM Verilog Instantiation Template
4. FIFO Parameterizable Macros x
4.1. Asynchronous FIFO Parameterizable Macros 4.2. Synchronous FIFO Parameterizable Macros
4.1. Asynchronous FIFO Parameterizable Macros x
4.1.1. Asynchronous FIFO Port Descriptions 4.1.2. Asynchronous FIFO Parameters 4.1.3. Asynchronous FIFO VHDL Instantiation Template 4.1.4. Asynchronous FIFO Verilog Instantiation Template
4.2. Synchronous FIFO Parameterizable Macros x
4.2.1. Synchronous FIFO Port Descriptions 4.2.2. Synchronous FIFO Parameters 4.2.3. Synchronous FIFO VHDL Instantiation Template 4.2.4. Synchronous FIFO Verilog Instantiation Template
1. Answers to Top FAQs
2. Parameterizable Macros for Intel FPGAs Overview
3. Dual-Port Random Access Memory (RAM) Parameterizable Macros
4. FIFO Parameterizable Macros
5. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide
6. Parameterizable Macros for Intel FPGAs User Guide Archives

4. FIFO Parameterizable Macros

The FIFO is First-in First-out, meaning that words written first in the FIFO are read back first. The FIFO acts as a temporary memory where you can write data and read it back later. You can apply the FIFO functions in data buffering applications that comply with the first-in-first-out data flow in synchronous or asynchronous clock domains. SYNC_FIFO/sync_fifo is a synchronous FIFO that uses the same clock signal to perform the read and write operations. ASYNC_FIFO/async_fifo is an asynchronous FIFO that uses the rdclk or wrclk signal to perform the read or write operation, respectively.

You can instantiate the parameterizable SYNC_FIFO/sync_fifo and ASYNC_FIFO/async_fifo modules using the instantiation templates available in Intel® Quartus® Prime Pro Edition software, starting from version 23.1. You can instantiate the SYNC_FIFO/sync_fifo module using the synchronous FIFO template (sync_fifo or SYNC_FIFO). You can instantiate the ASYNC_FIFO/async_fifo module using the asynchronous FIFO template (async_fifo or ASYNC_FIFO).

This section provides the block diagrams, port descriptions, parameter tables, and instantiation templates of the SYNC_FIFO/sync_fifo and ASYNC_FIFO/async_fifo macro modules. For more information on these FIFO modules, such as the timing requirements, metastability protection, and operating modes, refer to the FIFO Intel FPGA IP User Guide.


Section Content
Asynchronous FIFO Parameterizable Macros
Synchronous FIFO Parameterizable Macros

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