3.2.2. True Dual-Port RAM Parameters
Name | Allowed Values | Description |
---|---|---|
ADDR_WIDTH_A | Device and DATA_WIDTH_A dependent | Specifies the width of the usedw port. The default value is 11. |
ADDR_WIDTH_B | Device and DATA_WIDTH_B dependent | Specifies the width of the usedw port. The default value is 11. |
BYTE_EN_WIDTH_A | 1 | Width of the byte enable bus at Port A. The width for BYTE_EN_WIDTH_A should be equal to DATA_WIDTH_A divided by BYTE_SIZE. |
BYTE_EN_WIDTH_B | 1 | Width of the byte-enable bus at Port B. This width should be equal to DATA_WIDTH_B divided by BYTE_SIZE. |
BYTE_SIZE | 5 8 9 10 |
Specifies the size of the byte for byte-enable mode. |
IN_CLK_EN_A | NORMAL BYPASS |
Specifies the clock enable for the input registers of Port A. |
IN_CLK_EN_B | NORMAL BYPASS |
Specifies the clock enable for the input registers of Port B. |
OUT_CLK_EN_A | NORMAL BYPASS |
Specifies the clock enable for the output registers of Port A. |
OUT_CLK_EN_B | NORMAL BYPASS |
Specifies the clock enable for the output registers of Port B. |
DATA_WIDTH_A | Device and ADDR_WIDTH_A dependent | Specifies the width of the data and q ports. The default value is 8. |
DATA_WIDTH_B | Device and ADDR_WIDTH_B dependent | Specifies the width of the data and q ports. The default value is 8. |
INIT_FILE_LAYOUT | PORT_A PORT_B |
Specifies the layout of the initialization file. |
MAX_DEPTH | 2048 | Specifies the depth of the RAM slices. |
INIT_FILE | *.mif *.hex |
Specifies the initialization file. |
OUT_DATA_ACLR_A | NONE CLEAR0 |
Asynchronous clear choice for data output registers at Port A. When OUT_DATA_REG_CLK_A is set to UNREGISTERED, this parameter specifies the clearing parameter for the output latch. |
OUT_DATA_SCLR_A | NONE SCLEAR |
Synchronous clear choice for data output registers at Port A. When OUT_DATA_REG_CLK_A is set to UNREGISTERED, this parameter specifies the clearing parameter for the output latch. |
OUT_DATA_ACLR_B | NONE CLEAR0 |
Asynchronous clear choice for data output registers at Port B. When OUT_DATA_REG_CLK_B is set to UNREGISTERED, this parameter specifies the clearing parameter for the output latch. |
OUT_DATA_SCLR_B | NONE SCLEAR |
Synchronous clear choice for data output registers at Port B. When OUT_DATA_REG_CLK_B is set to UNREGISTERED, this parameter specifies the clearing parameter for the output latch. |
OUT_DATA_REG_CLK_A | UNREGISTERED CLOCK1 CLOCK0 |
Clock choice for data output registers at Port A. |
OUT_DATA_REG_CLK_B | UNREGISTERED CLOCK1 CLOCK0 |
Clock choice for data output registers at Port B. |
READ_DURING_WRITE_MODE_A | NEW_DATA_NO_NBE_READ |
The behavior of read-during-write mode in Port A. |
READ_DURING_WRITE_MODE_B | NEW_DATA_NO_NBE_READ |
The behavior of read-during-write mode in Port B. |