Visible to Intel only — GUID: cri1658396042769
Ixiasoft
Visible to Intel only — GUID: cri1658396042769
Ixiasoft
2.5.3. VREF Sources and Input Standards Grouping
M-Series devices support internal VREF sources. Each I/O lane in the bank also has its own internal VREF generator. You can configure VREF generator in the External Memory Interfaces Intel® FPGA IP and PHY Lite for Parallel Interfaces Intel® FPGA IP.
In each I/O lane, adhere to the input standards grouping to ensure all input pins in the I/O lane use the same internal VREF source. If the mix of input standards in an I/O lane does not adhere to these groupings, Quartus® Prime displays error messages during design compilation.
Group | Input Standards Mix within I/O Lane |
---|---|
Group 1 |
|
Group 2 |
|
Group 3 |
|
Group 4 |
|
Group 5 |
|