Visible to Intel only — GUID: rrh1658580773039
Ixiasoft
Visible to Intel only — GUID: rrh1658580773039
Ixiasoft
6.4. GPIO Intel® FPGA IP Interface Signals
Signal Name | Direction | Description |
---|---|---|
pad_in[SIZE-1:0] | Input | Input signal from the pad. |
pad_in_b[SIZE-1:0] | Input | Negative node of the differential input signal from the pad. This port is available if you turn on the Use differential buffer option. |
pad_out[SIZE-1:0] | Output | Output signal to the pad. |
pad_out_b[SIZE-1:0] | Output | Negative node of the differential output signal to the pad. This port is available if you turn on the Use differential buffer option. |
pad_io[SIZE-1:0] | Bidirectional | Bidirectional signal connection with the pad. |
pad_io_b[SIZE-1:0] | Bidirectional | Negative node of the differential bidirectional signal connection with the pad. This port is available if you turn on the Use differential buffer option. |
Signal Name | Direction | Description |
---|---|---|
din[DATA_SIZE-1:0] | Input | Data input from the FPGA core in output or bidirectional mode. DATA_SIZE depends on the register mode:
|
dout[DATA_SIZE-1:0] | Output | Data output to the FPGA core in input or bidirectional mode, DATA_SIZE depends on the register mode:
|
oe[OE_SIZE-1:0] | Input | OE input from the FPGA core in output mode with Enable output enable port turned on, or bidirectional mode. OE is active high. When transmitting data, set this signal to 1. When receiving data, set this signal to 0. OE_SIZE depends on the register mode:
|
Signal Name | Direction | Description |
---|---|---|
ck | Input | In input and output paths, this clock feeds a packed register or DDIO. In bidirectional mode, this clock is the unique clock for the input and output paths if you turn off the Separate input/output Clocks parameter. |
ck_in | Input | In bidirectional mode, these clocks feed a packed register or DDIO in the input and output paths if you turn on the Separate input/output Clocks parameter. |
ck_out | ||
cke | Input | Clock enable. |
Signal Name | Direction | Description |
---|---|---|
sclr | Input | Synchronous clear input. Not available if you select None or Preset for the Enable synchronous clear / preset port option. |
aclr | Input | Asynchronous clear input. Active high. Not available if you select None or Preset for the Enable asynchronous clear / preset port option. |
aset | Input | Asynchronous set input. Active high. Not available if you select None or Clear for the Enable asynchronous clear / preset port option. |
sset | Input | Synchronous set input. Not available if you select None or Clear for the Enable synchronous clear / preset port option. |