FPGA AI Suite: Compiler Reference Manual

ID 768972
Date 9/06/2024
Public
Document Table of Contents

3.2. Generating Artifacts for Memoryless Operation

When a graph is compiled with an architecture file that has the enable_parameter_rom FPGA AI Suite IP block configuration option enabled, the FPGA AI Suite compiler (dla_compiler) produces a set of memory initialization (.mif) files in the current working directory. These files are required to build the bitstream for memoryless operation and to run software inference. You do not need to specify any additional compiler options when compiling an architecture with memoryless operation enabled.

For an architecture with memoryless operation enable, the compiler produces the following files:
  • ./memoryless_filter_hw*.mif

    Contain the graph filters that are used to build the bitstream for memoryless operation.

  • ./memoryless_bias_scale_hw*.mif

    Contain the graph biases and scaling factors used to build the bitstream for memoryless operation

  • ./memoryless_filter_ref*.mif

    Contain the graph filters in software-reference form.

  • ./memoryless_bias_scale_ref*.mif

    Contains the graph biases and scaling factors in software-reference format

  • ./memoryless_config.mif

    Stores the FPGA AI Suite instructions for the compiled graph.

The filter and bias/scale .mif files are postfixed with an integer that represents the PE that the parameters are loaded into.