FPGA AI Suite: Compiler Reference Manual

Download PDF
ID 768972
Date 9/06/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. FPGA AI Suite Compiler Reference Manual 2. About the FPGA AI Suite Compiler 3. FPGA AI Suite Compiler Use Modes 4. FPGA AI Suite Compiler Command Line Options 5. Compiler Inputs and Outputs A. FPGA AI Suite Compiler Reference Manual Archives B. FPGA AI Suite Compiler Reference Manual Document Revision History
3. FPGA AI Suite Compiler Use Modes x
3.1. Compiling a Graph 3.2. Generating Artifacts for DDR-Free Operation 3.3. Estimating the Performance of a Graph 3.4. Estimating the Area of an Architecture 3.5. Generating an Optimized Architecture
3.5. Generating an Optimized Architecture x
3.5.1. Generating an Architecture for Highest Performance 3.5.2. Generating an Architecture Optimized for a Frame Rate Target Value
4. FPGA AI Suite Compiler Command Line Options x
4.1. Inputs (dla_compiler Command Options) 4.2. Outputs (dla_compiler Command Options) 4.3. Reporting (dla_compiler Command Options) 4.4. Compilation Options (dla_compiler Command Options) 4.5. Architecture Options (dla_compiler Command Options) 4.6. Architecture Optimizer Options (dla_compiler Command Options) 4.7. Analyzer Tool Options (dla_compiler Command Options) 4.8. Miscellaneous Options (dla_compiler Command Options)
5. Compiler Inputs and Outputs x
5.1. FPGA AI Suite Input File Formats 5.2. FPGA AI Suite Compiler Graph Export Formats 5.3. The Partitioning Table Report 5.4. Model Analyzer Reports
1. FPGA AI Suite Compiler Reference Manual
2. About the FPGA AI Suite Compiler
3. FPGA AI Suite Compiler Use Modes
4. FPGA AI Suite Compiler Command Line Options
5. Compiler Inputs and Outputs
A. FPGA AI Suite Compiler Reference Manual Archives
B. FPGA AI Suite Compiler Reference Manual Document Revision History

5.4. Model Analyzer Reports

During compilation, the FPGA AI Suite compiler analyzes your model and generates a series reports:
  • Model analyzer report

    The model analyzer report (model_analyzer_report.txt) contains information about the model, the layer placement information, the reason why layers were unsupported, and how internal layers relate to the layers from the original OpenVINO™ graph passed to the FPGA AI Suite compiler.

  • Unsupported layer chains report

    The unsupported layer chains report (unsupported_layer_chains.dot) contains a visual representation of the unsupported layers of the model.

    The report is structured to highlight nodes as follows:
    • Nodes that are directly unsupported by the FPGA AI Suite compiler are highlighted in red.
    • Nodes that are unsupported due to other nodes being unsupported are highlighted in orange.
    • Nodes from the original model that have been unsupported are highlighted in blue.
    Trace from any unsupported node in the original graph to find the root causes of lack of support.
    You can convert this report to SVG format which can be displayed in a web browser by running the following command: 
    dot -Tsvg unsupported_layer_chains.dot -o unsupported_layer_chains.svg
  • Per-layer latency report
    This report is generated only if you specified one or both of the following FPGA AI Suite compiler command options:
    • --fanalyze-performance
    • --festimate-per-layer-latencies
    The per-layer latency report (per_layer_latency_report.txt) reports information about the estimated throughput on three levels of granularity:
    • The clock cycle count for the graph as a whole
    • The clock cycle count for each of the subgraphs
    • The clock cycle count for each layer in the graph.

    The per-layer clock cycle information is accompanied by the internal layer name, and the original layer names from the OpenVINO™ graph that map to each of the internal layer.

Level Two Title