FPGA AI Suite: Compiler Reference Manual

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ID 768972
Date 9/06/2024
Public
Document Table of Contents
Document Table of Contents x
1. FPGA AI Suite Compiler Reference Manual 2. About the FPGA AI Suite Compiler 3. FPGA AI Suite Compiler Use Modes 4. FPGA AI Suite Compiler Command Line Options 5. Compiler Inputs and Outputs A. FPGA AI Suite Compiler Reference Manual Archives B. FPGA AI Suite Compiler Reference Manual Document Revision History
3. FPGA AI Suite Compiler Use Modes x
3.1. Compiling a Graph 3.2. Generating Artifacts for DDR-Free Operation 3.3. Estimating the Performance of a Graph 3.4. Estimating the Area of an Architecture 3.5. Generating an Optimized Architecture
3.5. Generating an Optimized Architecture x
3.5.1. Generating an Architecture for Highest Performance 3.5.2. Generating an Architecture Optimized for a Frame Rate Target Value
4. FPGA AI Suite Compiler Command Line Options x
4.1. Inputs (dla_compiler Command Options) 4.2. Outputs (dla_compiler Command Options) 4.3. Reporting (dla_compiler Command Options) 4.4. Compilation Options (dla_compiler Command Options) 4.5. Architecture Options (dla_compiler Command Options) 4.6. Architecture Optimizer Options (dla_compiler Command Options) 4.7. Analyzer Tool Options (dla_compiler Command Options) 4.8. Miscellaneous Options (dla_compiler Command Options)
5. Compiler Inputs and Outputs x
5.1. FPGA AI Suite Input File Formats 5.2. FPGA AI Suite Compiler Graph Export Formats 5.3. The Partitioning Table Report 5.4. Model Analyzer Reports
1. FPGA AI Suite Compiler Reference Manual
2. About the FPGA AI Suite Compiler
3. FPGA AI Suite Compiler Use Modes
4. FPGA AI Suite Compiler Command Line Options
5. Compiler Inputs and Outputs
A. FPGA AI Suite Compiler Reference Manual Archives
B. FPGA AI Suite Compiler Reference Manual Document Revision History

3.1. Compiling a Graph

For compiling a graph, use the following dla_compiler command options:
Option Description
--network-file [Required] The path to the OpenVINO™ Inference Engine network topology (.xml) file or files. If you have multiple files, list them as a sequence of space-delimited arguments.

The .bin weights file must be in the same directory as the .xml file, and the file must have the same file name (except for the .bin extension).

--march [Required] The architecture parameterization to use when compiling the graph.
--plugins-file [Optional] The location of the plugins.xml file.
--batch-size [Optional] Override the network batch size.
--bin-data [Optional] Forces graph to be compiled for binary data input, regardless of input tensor shape. Binary data is read as the input layer type.

Otherwise, graphs with 1- or 3-channel inputs are converted to U8 inputs and binary input files are discarded.

--ffolding-option [Optional] Controls how (or if) folding happens on the first convolution layer.
--o [Optional] File name of the exported compiled graph when using open_vino_hetero format.
--dumpdir [Optional] Directory for dumping additional debug output.
--foutput-format [Optional] Specifies the export format:
open_vino_hetero
The open_vino_hetero format dumps the graph from the OpenVINO™ level. Choose this format for use with the supplied example designs.
dla_compiled_result
The dla_compiled_result format dumps the configuration and weights buffer. Do not use this format unless you are writing your own network import routines.
--fplugin [Optional] Specifies the OpenVINO™ plugins. Typically set to HETERO:FPGA,CPU, which first tries to use the FPGA IP to implement each portion of the graph and falls back onto the host CPU only for portions that the FPGA IP does not support.
The simplest dla_compiler command format for compiling a graph is as follows: 
dla_compiler \
   --network-file <list of  OpenVINO IR XML files> \
   --march <path to .arch file>

Example Command

dla_compiler \
  --network-file ResNet50.xml \
  --march $COREDLA_ROOT/example_architectures/A10_Generic.arch
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