FPGA AI Suite: Compiler Reference Manual

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ID 768972
Date 9/06/2024
Public
Document Table of Contents
Document Table of Contents x
1. FPGA AI Suite Compiler Reference Manual 2. About the FPGA AI Suite Compiler 3. FPGA AI Suite Compiler Use Modes 4. FPGA AI Suite Compiler Command Line Options 5. Compiler Inputs and Outputs A. FPGA AI Suite Compiler Reference Manual Archives B. FPGA AI Suite Compiler Reference Manual Document Revision History
3. FPGA AI Suite Compiler Use Modes x
3.1. Compiling a Graph 3.2. Generating Artifacts for DDR-Free Operation 3.3. Estimating the Performance of a Graph 3.4. Estimating the Area of an Architecture 3.5. Generating an Optimized Architecture
3.5. Generating an Optimized Architecture x
3.5.1. Generating an Architecture for Highest Performance 3.5.2. Generating an Architecture Optimized for a Frame Rate Target Value
4. FPGA AI Suite Compiler Command Line Options x
4.1. Inputs (dla_compiler Command Options) 4.2. Outputs (dla_compiler Command Options) 4.3. Reporting (dla_compiler Command Options) 4.4. Compilation Options (dla_compiler Command Options) 4.5. Architecture Options (dla_compiler Command Options) 4.6. Architecture Optimizer Options (dla_compiler Command Options) 4.7. Analyzer Tool Options (dla_compiler Command Options) 4.8. Miscellaneous Options (dla_compiler Command Options)
5. Compiler Inputs and Outputs x
5.1. FPGA AI Suite Input File Formats 5.2. FPGA AI Suite Compiler Graph Export Formats 5.3. The Partitioning Table Report 5.4. Model Analyzer Reports
1. FPGA AI Suite Compiler Reference Manual
2. About the FPGA AI Suite Compiler
3. FPGA AI Suite Compiler Use Modes
4. FPGA AI Suite Compiler Command Line Options
5. Compiler Inputs and Outputs
A. FPGA AI Suite Compiler Reference Manual Archives
B. FPGA AI Suite Compiler Reference Manual Document Revision History

3.3. Estimating the Performance of a Graph

To estimate the performance of a graph on an architecture, use the --fanalyze-performance dla_compiler command option.

The dla_compiler command compiles the graph for the specified architecture to estimate its performance. The performance estimator assumes that any portions of the graph that are assigned to the CPU run inference with zero latency. That is, the performance estimate accounts only for the FPGA portions of the graph.

The performance estimator also estimates the average memory bandwidth and the memory requirements of the graph. The estimated memory requirement is typically an underestimate because the memory estimates assume one input buffer and one output buffers while the FPGA AI Suite runtime uses a default of five of each.

The list of required and optional arguments includes all the required and optional arguments from Compiling a Graph . In addition, the following options are specific to estimating graph performance:

Option

Description
--fanalyze-performance [Required] Enables the performance estimator.
--fassumed-fmax-core= <assumed fMAX> [Optional] Specifies the assumed fMAX of the compiled FPGA AI Suite IP.

The performance estimator does not have the ability to estimate fMAX of a given IP parameterization, nor does it know which speed grade the IP targets. Typically, the IP achieves 300 MHz or higher on a C2 Arria® 10 device.

The default fMAX depends on the device family:
  • Arria® 10 - 265 MHz
  • Agilex™ 5 - 350 MHz
  • Agilex™ 7 - 500 MHz
  • Cyclone® 10 GX - 265 MHz
  • Stratix® 10 - 265 MHz
--fdump-performance-report [Optional] An optional output file for the performance estimate, otherwise the performance summary is displayed on the terminal.

The simplest dla_compiler command format for estimating the performance of a graph is as follows: 

dla_compiler \
   --network-file <path to graph.xml> \
   --march <path to .arch file> \
   --fanalyze-performance

Example Command

dla_compiler \
   --network-file ResNet50.xml ResNet101.xml \
   --march $COREDLA_ARCH/example_architectures/A10_Generic.arch \
   --fanalyze-performance \
   --fassumed-fmax-core=300
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