FPGA AI Suite: Compiler Reference Manual

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ID 768972
Date 9/06/2024
Public
Document Table of Contents
Document Table of Contents x
1. FPGA AI Suite Compiler Reference Manual 2. About the FPGA AI Suite Compiler 3. FPGA AI Suite Compiler Use Modes 4. FPGA AI Suite Compiler Command Line Options 5. Compiler Inputs and Outputs A. FPGA AI Suite Compiler Reference Manual Archives B. FPGA AI Suite Compiler Reference Manual Document Revision History
3. FPGA AI Suite Compiler Use Modes x
3.1. Compiling a Graph 3.2. Generating Artifacts for DDR-Free Operation 3.3. Estimating the Performance of a Graph 3.4. Estimating the Area of an Architecture 3.5. Generating an Optimized Architecture
3.5. Generating an Optimized Architecture x
3.5.1. Generating an Architecture for Highest Performance 3.5.2. Generating an Architecture Optimized for a Frame Rate Target Value
4. FPGA AI Suite Compiler Command Line Options x
4.1. Inputs (dla_compiler Command Options) 4.2. Outputs (dla_compiler Command Options) 4.3. Reporting (dla_compiler Command Options) 4.4. Compilation Options (dla_compiler Command Options) 4.5. Architecture Options (dla_compiler Command Options) 4.6. Architecture Optimizer Options (dla_compiler Command Options) 4.7. Analyzer Tool Options (dla_compiler Command Options) 4.8. Miscellaneous Options (dla_compiler Command Options)
5. Compiler Inputs and Outputs x
5.1. FPGA AI Suite Input File Formats 5.2. FPGA AI Suite Compiler Graph Export Formats 5.3. The Partitioning Table Report 5.4. Model Analyzer Reports
1. FPGA AI Suite Compiler Reference Manual
2. About the FPGA AI Suite Compiler
3. FPGA AI Suite Compiler Use Modes
4. FPGA AI Suite Compiler Command Line Options
5. Compiler Inputs and Outputs
A. FPGA AI Suite Compiler Reference Manual Archives
B. FPGA AI Suite Compiler Reference Manual Document Revision History

4.6. Architecture Optimizer Options (dla_compiler Command Options)

--interleave-search Option

Syntax
--interleave-search
Description
This option causes the architecture optimizer to evaluate different legal feature and filter interleave options. This significantly increases the run time of the architecture optimizer, by as much as 50%.

Due to the run time penalty, after an optimal interleave has been found for a given graph, the recommendation is to place the optimized interleave into the initial input .arch file and avoid using --interleave-search during any future fine-tuning.

For more information, refer to "Parameter group: pe_array" topic of FPGA AI Suite IP Reference Manual .

Default Value
N/A
Example
--interleave-search
Parsed As
(bool)

--mmax-resources Option

Syntax
--mmax-resources=<max_ALMs>,<max_M20Ks>,<max_DSPs>
Description
This option specifies the maximum number of ALMs, M20Ks, and DSPs to use when optimizing the architecture.

If you do not specify this option, the architecture uses as many resources as needed. In rare cases, the optimizer might use more resources than are available on the FPGA device.

Default Value
N/A
Example
--mmax-resources=50000,500,400
Parsed As
(vector<int>)
The vector must be of length 3. The int values can be separated by one of the following characters:
  • ,
  • ;
  • |
  • \

--mmax-resources-alm-util Option

Syntax
--mmax-resources-alm-util=<percent_alm_utilization>
Description
Set this option only if you also set the --mmax-resources option.

This option sets a percentage target of the <max_ALMs> value from the --mmax-resources option that architecture optimizer aims to use for the architecture. The remaining ALMs are used by the Quartus® Prime software to improve timing closure.

Valid values for this option are integers in the 1-100 range.

Default Value
100
Example
--mmax-resources-alm-util=75
Parsed As
(int)

--mtarget-fps Option

Syntax
--mtarget-fps=<target_framerate>
Description
This option specifies the target frame rate (fps) for an architecture optimized for minimum resource usage.

The architecture optimizer can use in excess of 100GB of RAM when using this option, and thus requires a server-class machine.

To reduce the number of threads and memory used by the architecture optimizer when you use the --mtarget-fps, set the COREDLA_TARGET_FPS_THREAD_LIMIT environment variable to specify the maximum number of threads to use. For example, issuing a export COREDLA_TARGET_FPS_THREAD_LIMIT=1 command, limits the architecture optimizer to running on one thread. Limiting the number of threads reduces the computational parallelism and can increase the runtime of the architecture optimizer.

Example
--mtarget-fps=25.0
Parsed As
(double)

--network-weighting Option

Syntax
--network-weighting="<network_weight_1> <network_weight_2> <network_weight_3>...<network_weight_n>"
Description
This option defines the relative optimization weighting of input graphs.
For example, if two graphs are specified and have throughput values of fps1 and fps2 , then the overall throughput is maximized using the user-specified weights w1 and w2 as follows:

When you specify multiple networks, the list of weights must be space-delimited.

If this option is not specified, all networks are equally weighted.

Example
--network-weightings="1 2"
Parsed As
(vector<int>)
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